Program execution, by default, proceeds sequentially. The program counter (PC) register plays an important role in managing the control flow. At a simple level, the PC can be thought of as pointing to the next instruction. The processor fetches the instruction at the address pointed to by the PC. When an instruction is fetched, the PC is automatically incremented to point to the next instruction. If we assume that each instruction takes exactly four bytes as in MIPS and SPARC processors, the PC is automatically incremented by four after each instruction fetch. This leads to the default sequential execution pattern. However, sometimes we want to alter this default execution flow. In high-level languages, we use control structures such asif-then-elseand while statements to alter the execution behavior based on some run-time conditions. Similarly, the procedure call is another way we alter the sequential execution. In this section, we describe how processors support flow control. We look at both branch and procedure calls next.
Branching
Branching is implemented by means of a branch instruction. There are two types of branches: direct and indirect. The direct branch instruction carries the address of the target instruction explicitly. In indirect branch, the target address is specified indirectly via either memory or a register. We look at an indirect branch example in Chapter 14 (page 259). In the rest of this section, we consider direct branches.
jump target instruction y instruction z instruction x instruction b instruction c target: instruction a
Figure 2.3Normal branch execution.
We can divide the branches into two categories: unconditional and conditional. In both cases, the transfer control mechanism remains the same as that shown in Figure 2.3. Unconditional Branch The simplest of the branch instructions is the unconditional branch, which transfers control to the specified target. Here is an example branch in- struction:
branch target
Specification of the target address can be done in one of two ways: absolute address or PC-relative address. In the former, the actual address of the target instruction is given. In the PC-relative method, the target address is specified relative to the PC contents. Most processors support absolute address for unconditional branches. Others support both for- mats. For example, MIPS processors support absolute address-based branch by
j target
and PC-relative unconditional branch by
b target
In fact, the last instruction is an assembly language instruction; the processor supports only thejinstruction.
The PowerPC allows each branch instruction to use either an absolute or a PC-relative address. The instruction encoding has a bit—called the absolute address (AA) bit—to indicate the type of address. If AA = 1, absolute address is assumed; otherwise, the PC- relative address is used.
If the absolute address is used, the processor transfers control by simply loading the specified target address into the PC register. If PC-relative addressing is used, the specified target address is added to the PC contents, and the result is placed in the PC. In either
24 Guide to RISC Processors
case, because the PC indicates the next instruction address, the processor will fetch the instruction at the intended target address.
The main advantage of using the PC-relative address is that we can move the code from one block of memory to another without changing the target addresses. This type of code is calledrelocatable code. Relocatable code is not possible with absolute addresses. Conditional Branch In conditional branches, the jump is taken only if a specified con- dition is satisfied. For example, we may want to take a branch if the two values are equal. Such conditional branches are handled in one of two basic ways.
• Set-Then-Jump: In this design, testing for the condition and branching are sepa- rated. To achieve communication between these two instructions, a condition code register is used. The PowerPC follows this design, which uses a condition register to record the result of the test condition. It uses a compare (cmp) instruction to test the condition. This instruction sets the various condition bits to indicate the rela- tionship between the two compared values. The following code fragment, which compares the values in registersr2andr3, should clarify this sequence.
cmpd r2,r3 ; compare the two values in r2 and r3
bne target ; if r2=r3, transfer control to target
not r3,r3 ; if r2=r3, this instruction is executed
. . . target:
add r4,r3,r4 ; control is transferred here if r2=r3
. . .
The bne(branch if not equal) instruction transfers control totargetonly if the two values in registersr2andr3are not equal.
• Test-and-Jump: In this method, testing and branching are combined into a single instruction. We use the MIPS to illustrate the principle involved in this strategy. The MIPS architecture supports several branch instructions that test and branch (for a quick peek, see Table 14.2 on page 249). For example, the branch on not equal instruction
bne Rsrc1,Rsrc2,target
tests the contents of the two registersRsrc1andRsrc2for equality and transfers control to target if Rsrc1 = Rsrc2. If we assume that the numbers to be compared are in registers$t0and$t1, we can write the branch instruction as
bne $t1,$t0,target
This single instruction replaces the two-instructioncmp/bnesequence used by the PowerPC.
jump target instruction y instruction z instruction x instruction b instruction c target: instruction a
Figure 2.4Delayed branch execution.
Some processors maintain registers to record the condition of the arithmetic and logi- cal operations. These are calledcondition code registers.These registers keep a record of the status of the last arithmetic/logical operation. For example, when we add two 32-bit integers, it is possible that the sum might require more than 32 bits. This is the overflow condition that the system should record. Normally, a bit in the condition code register is set to indicate this overflow condition. The MIPS, for example, does not use a condition register. Instead, it uses exceptions to flag the overflow condition. On the other hand, Pow- erPC and SPARC processors use condition registers. In the PowerPC, this information is maintained by the XER register. SPARC uses a condition code register.
Some instruction sets provide branches based on comparisons to zero. Some examples that provide this type of branch instructions include the MIPS and SPARC (see Table 14.3 on page 250 for the MIPS instructions).
Highly pipelined RISC processors support what is known as delayed branch execu- tion. To see the difference between delayed and normal branch execution, let us look at the normal branch execution shown in Figure 2.3. When the branch instruction is executed, control is transferred to the target immediately.
In delayed branch execution, control is transferred to the target after executing the instruction that follows the branch instruction. For example, in Figure 2.4, before the con- trol is transferred, the instruction instruction y(shown shaded) is executed. This instruction slot is called the delay slot. For example, MIPS and SPARC use delayed branch execution. In fact, they also use delayed execution for procedure calls.
Why does the delayed execution help? The reason is that by the time the processor decodes the branch instruction, the next instruction is already fetched. Thus, instead of throwing it away, we improve efficiency by executing it. This strategy requires reordering of some instructions. In Chapter 5 we give some examples of how it affects the programs.
26 Guide to RISC Processors instruction x call procA instruction y instruction z procA: instruction a instruction b instruction c return Called procedure Calling procedure . . . . . .
Figure 2.5Control flow in procedure calls.