Photons produced by the Cherenkov radiation of charged particles were detected by the 9456 Hamamatsu R1408 20 cm PMTs surrounding the AV. Single photoelectrons are amplified through the dynode stages creating a measurable charge pulse. The goal of the electronics was to read out the charge and time of the pulse each time a PMT fires.
The front end electronics were contained within 19 crates sitting on a deck above the detector. Each crate instrumented 512 PMT channels. The PMT Interface Card (PMTIC) provided the high voltage and receives the signal from 32 PMTs. They were then processed in the Front End Cards (FECs). Each FEC contained
four daughterboards (DB), which each handle eight channels. The DB contained three kinds of custom application specific integrated circuits (ASICs) that applied a threshold to the PMT signal, integrated the charge of the pulse, and measured the relative time of the hits. The charge was measured with two different gains over two different length time windows, approximately 60 ns and 390 ns long.
In addition to channel by channel thresholds, there was a detector wide trigger threshold in order to limit the amount of data read out. Each time a PMT signal crossed its threshold, four different pulses were sent to the trigger system to be summed: a 20 ns and a 100 ns square pulse, and a low and high gain shaped PMT pulse. The trigger pulses from all channels were summed on the analog trigger boards (MTCAs), and then those that cross a set threshold were sent on to the digital trigger board (MTCD). The MTCD checked the fired triggers against a mask to determine whether to send a detector wide “global trigger” that would tell all the front end electronics to save and read out all PMT pulses recorded for a time window around it. For physics analyses, the trigger signal used was the sum of the 100 ns square pulses, called NHIT100.
When the front end received the global trigger signal, the integrated charges and time measurement were stored in each channel’s 16 cell analog memory. The FEC then iterated through the hit channels and digitized the signals using four 12 bit ADCs. The digitized charges were then stored in 4 MB of RAM located on the FEC, along with a trigger id that could be matched to information read out from the MTCD about the trigger type and time. The data was read out through a central computer, which was connected to a VME crate through a Motorola 68040 processor (eCPU). The VME crate was connected to the 19 front end crates through pairs of translator boards called XL1s and XL2s, which extended the VME address
Figure 6.2: The SNO front end electronics.
space so that the whole front end was memory mapped and could be read out directly from the DAQ computer. An overview of the DAQ is shown in Fig. 6.2.
6.3.1
SNO+ Upgrade
The SNO experiment was designed for a heavy water target with a high energy threshold. The expected detector trigger rate was tens of Hz, and the electronics could handle a max data rate of 2 Mb/s. A new experiment, SNO+, is being developed that will use the same detector but with a scintillator target. This allows SNO+ to have a much lower energy threshold than SNO, low enough to see even the lowest energy pp solar neutrinos. In addition, by adding tellurium to the target
it is possible to investigate whether neutrinos are Majorana or Dirac particles by looking for neutrinoless double beta decay.
Scintillation produces significantly more light than Cherenkov radiation, and SNO+ expects to get around 500 pe per MeV with a pure scintillator target, com- pared to about 8 for SNO. In addition, the energy threshold creates a much higher event rate. For this reason, the data acquisition electronics needed to be upgraded in order to handle the increased data rate.
The upgrade plan is shown in Fig. 6.3. The VME extending XL1 and XL2 translator boards are replaced with a new board called the XL3 that sits in each front end crate. Each XL3 reads out its own crate, then autonomously pushes the data over ethernet to the DAQ computer. We use a Virtex 4 FPGA with an embedded PowerPC to do most of the processing on the XL3. The FPGA holds a VHDL state machine that implements the front end crate’s custom SNOBUS protocol with very precise timing. The data is then passed over to the embedded processor, where we can use C code to easily control the ethernet output and any extra functionality. We implement a full TCP-IP stack using the light weight IP library (LWIP). In addition, the flexibility offered by programming in C allowed us to run most of the electronics testing and calibration software locally on each XL3. Each XL3 has a max data rate of around 14 MB/s, for a detector total of about 250 MB/s, which is equivalent to about 2 million PMT hits per second.