Marco contextual

There are several ideas or applications in which the low-swing signalling schemes proposed in this work can be used. There are a few suggestions such as increasing bandwidth or incorporating Silicon-on-Insulator technique into the design to further improve the performance and reduce power consumption of the proposed schemes. Subsequently, the proposed driver circuits can be implemented in applications such as multi-level signalling or adaptive signalling schemes to observe their abilities to provide improvements in delay and power consumption as well as reduced leakage currents and increased robustness against external disturbances and process variations, in the existing applications.

6.3.1. Increase bandwidth or operating frequency

The diffusive and dispersive effects of signals travelling over RC dominated on-chip interconnects limits both the transmission data rates and propagation latency in long global interconnects within microprocessor circuits [14]. A static driver with a low-impedance current sensing repeater is one of the techniques used to overcome this problem; it has a higher interconnect bandwidth compared to the full-swing voltage sensing schemes, but at the expense of increased power dissipation due to the current mode signalling. The proposed driver schemes in this work have been shown to have a significant improvement in power consumption at a maximum operating frequency of 1GHz. Larger operating frequencies are

required to achieve high signal bandwidth. However, as the operating frequency reaches beyond 1GHz, disruption in signal data can

occur, which disrupts the efforts in increasing the signal bandwidth using the proposed drivers. As the demand for high data bandwidth becomes more important in the deep submicron regime, it is essential to modify the proposed driver circuits by incorporating additional mechanisms which enable them to transmit high data bandwidth with low power consumption on the global interconnect lines.

179 6.3.2. Multi-level signalling application

The multi-level signalling system [15] operates in current mode and consists of a transmitter, receiver and decoder where the transmitter encodes the two signal bits into four current levels and transmits them. The receiver compares the transmitted currents with the reference currents, which converts the four current levels into thermometer codes. The decoder then recovers the original signal. This approach is known to provide high bandwidth and comparable delay to the buffer insertion techniques, it also reduces the number of interconnect wires as with this technique, multiple bits can be transmitted on a single wire. However, this approach does have its limitations as it relies on matching and proper sizing of the driver and receiver transistors and is thus prone to the effects of process variations. The proposed drivers can be incorporated into this system as they have been shown to be more robust against process variations and matching-related noise, and at the same time, the bandwidth of the proposed driver schemes can be improved with this system. Subsequently, the proposed drivers having a diode-connected configuration at the output can easily be transformed to encapsulate similar functions as current mirrors changing the driver from operating in voltage mode to current mode. Since the system requires constant difference between the current levels produced by the drivers for the system to function properly, the modified part of the proposed drivers can be tuned to achieve this. This can be carried out by changing the size of the diode-connected transistors at the output of the drivers, giving off different current levels for each driver. However, it is important to make the necessary changes in the proposed receiver circuit in order to avoid any mismatch between them. 6.3.3. Implementation of the designs using Silicon on Insulator (SoI) Technology

Silicon-on-Insulator (SOI) is a semiconductor fabrication technique which uses pure crystal silicon and silicon oxide for integrated circuits. This technology is useful in the area where there are increased effects of process variation and reduced immunity of SEUs. It has attracted attention to be the next force behind technology scaling due to its capability to provide more speed, less power consumption and enhanced scalability as demanded by future

CMOS generations. Comparing the bulk CMOS and SOI technologies, SOI can work at a 20

to 35% higher speed than standard CMOS, as well as having 2 to 4 times less power consumption when running under the same operating conditions. Another advantage of this technology is the suppressed short channel effects, which means that the SOI device has a

180 steeper sub-threshold slope which in turn can be translated into higher driver current and lower source/drain leakage current.

Although driver schemes proposed in this work employ a bulk CMOS technology they have shown vast improvements in speed, power consumption, leakage current and robustness to process variations and SEU. It is expected that by implementing this in SOI, this will result in more speed, less power consumption and leakage current and greater robustness against process variations and SEU effects than the current implementation. Subsequently, as SOI technology can be used to achieve these advantages, the complexity or area overhead of the proposed driver circuits can be reduced as the circuitry or mechanisms that were incorporated into the circuit design to reduce leakage currents and provide faster signalling can be removed, as they will no longer be necessary.

6.3.4. Adaptive signalling schemes

Previously, the results have shown that a trade-off is required between power consumption and delay, as well as between performance or power consumption and noise immunity for the proposed driver schemes, especially in the case of the nLVSD driver. This is because with the proposed driver schemes, low power consumption can be achieved and high speed signalling can be maintained with the low voltage swing but at the cost of noise immunity, even though it can still be considered as reliable, as the SNR is still above 1. However, it is necessary to improve the noise immunity of the proposed drivers especially the nLVSD circuit whilst maintaining low power consumption and high speed signalling. This can be done by employing an adaptive mechanism which varies the voltage swing, as well as an error protection mechanism which adaptively selecting error coding methods such as parity, Hamming and Berger codes, based on the noise levels and detected energy consumption. Typically, an adaptive signalling scheme is used to dynamically control the driver swing and the corresponding receiver threshold by applying dynamic voltage scaling to the interconnects in order to reduce the power consumption on the interconnect. Subsequently, the variable voltage swing can impact on the speed at which the driver is able to charge and discharge the load capacitance, thus the maximum reliable operating frequency is reduced with lower swings, thus also requiring an adaptive scheme for speed. However, if the proposed driver schemes are implemented, the adaptive scheme for speed can be discarded as

181 the proposed driver schemes have faster signalling even with lower voltage swings. Therefore, high operating frequency can still be achieved when using low voltage swing. However, operating with lower voltage swings makes the communication more sensitive to several noise sources. In order to cancel this effect, an error detection encoding at the source and Automatic Repeat Request (ARQ) strategy can be implemented [16]. It is known that error detection schemes with retransmission are less costly in terms of energy consumption than error correction schemes. A controller is required which decides on the voltage swing to be used and also to explore the design space for safe operating points. Inputs such as bandwidth requirements and channel reliability are required for controller.

Another adaptive scheme that can be incorporated into the system is adaptive error protection scheme. Different coding methods have different capabilities to detect errors induced by different noise sources. While the coding scheme adopted can be designed for the worst case noise scenario, such an approach will be inefficient in terms of both energy and performance. Therefore it is necessary to design a system with self-embedded intelligence that can vary the coding technique based on the noise behaviour, and switch to the least powerful error detection scheme that can maintain the undetected error rates below specified levels, while energy consumption can be minimized while maintaining required protection levels.

It would be beneficial to consider the two adaptive schemes as complementary and devise schemes that combine voltage scaling and code adaptation. Such a combination is relevant given that a number of different coding schemes can be implemented simultaneously; the number of supply voltages or voltage swing range is typically limited in real systems.

References

[1] C. Piguet, “Low-Power Electronics Design,” Computer Engineering, V. Oklobdzija, ed., Switzerland: CRC Press, 2005, pp. 159-161.

[2] A. Tajalli and Y. Leblebici, “A power-efficient LVDS driver circuit in 0.18um CMOS technology,” Research in Microelectonics and Electronics Conference, PRIME 2007, 2007, pp. 145-148.

[3] L. Yang, C. Jue-Ping, H. Yue, and L. Yi, “A low swing differential signalling circuit for on-chip global interconnects,” 9th International Conference on Solid-State and

182 [4] L. Zhang, J. Wilson, R. Bashirullah, L. Luo, J. Xu, and P. Franzon, “Driver pre-

emphasis techniques for on-chip global buses,” Proceedings of the 2005 International

Symposium on Low Power Electronics and Design, ISLPED ’05, 2005, pp. 186-191.

[5] H. Zhang, V. George, and J.M. Rabaey, “Low-swing on-chip signaling techniques: effectiveness and robustness,” IEEE Trans. Very Large Scale Integrated System, vol. 8, 2000, pp. 264-272.

[6] H. Song, S. Kim, and D.-K. Jeong, “A reduced-swing voltage-mode driver for low power multi-Gb/s transmitter,” Journal of Semiconductor Technology and Science, vol. 9, 2009, pp. 104-109.

[7] F.S. Q. Zhu P. Chong, “A Placement Technique for Multiple Voltage Design,” 2006. [8] U. of C. Berkeley, “BSIM4.3.0 MOSFET Model Userʼs Manual.”

[9] L. Zhang, J.M. Wilson, R. Bashirullah, L. Luo, J. Xu, and P.D. Franzon, “Voltage- Mode Driver Preemphasis Technique For On-Chip Global Buses,” Very Large Scale

Integration (VLSI) Systems, IEEE Transactions on, vol. 15, 2007, pp. 231-236.

[10] M. Ferretti and P.A. Beerel, “Low swing signaling using a dynamic diode-connected driver,” Proceedings of the 27th European Solid-State Circuits Conference. ESSCIRC

2001, 2001, pp. 369-372.

[11] W.J. Dally and J.W. Poulton, Digital Systems Engineering, Cambridge University Press, 1998.

[12] R.K. Iyer and D. Rosetti, “A statistical load dependency of CPU errors at SLAC,”

Twenty-Fifth International Symposium on Fault-Tolerant Computing, “ Highlights from Twenty-Five Years”., 1995, p. 373.

[13] H. Ball and F. Hardy, “Effects and detection of intermitten failures in digital system,”

Proc. AFIPS Conference, 1969, pp. 329-335.

[14] H.B. Bakoglu, Circuits, Interconnections and Packaging for VLSI, Reading: Addison- Wesley, 1990.

[15] V. Venkatraman and W. Burleson, “Impact of Process Variations on Multi-Level Signaling for On-Chip Interconnects,” Proceedings of the 18th International

Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, Washington, DC, USA: IEEE Computer Society, 2005,

pp. 362-367.

[16] F. Worm, P. Ienne, P. Thiran, and G.A.-de micheli de micheli G., “An adaptive low- power transmission scheme for on-chip networks,” 15th International Symposium on