105 1.6.6 Materiales de rodadura y deterioro vial

A system obeys the PL1 memory model if and only if for any PL1 program (defined above), all executions of the program on this system are sequentially consistent.

An interesting observation is that the above definition specifies the memory behavior for properly-labeled programs only; the behavior of programs that are not properly-labeled is unspecified. Of course, any practical implementation of the above model will have a specified behavior for all programs, regardless of whether the

2_{It is conceptually possible for an instruction in a program to never generate an operation in any SC execution. Naturally, the decision}

on whether the program is a PL1 program does not depend on the label on such instructions. Therefore, the programmer is free to use any label for such instructions.

READ/WRITE READ/WRITE READ WRITE READ/WRITE READ/WRITE READ READ/WRITE READ/WRITE WRITE 1 2 3 4 5 6 7

(a) program order

READ/WRITE READ/WRITE READ WRITE 1 2 3 READ READ/WRITE READ/WRITE WRITE 5 6 7 (b) sufficient order READ/WRITE READ/WRITE 4

Figure 3.5: Possible reordering and overlap for PL1 programs.

program is properly-labeled. Nevertheless, the above under-specification provides implementations with an extra flexibility in the behavior they support for non-PL programs.

Possible Optimizations for PL1

As we discussed in Chapter 2, a simple and sufficient way to maintain sequential consistency is to (i) execute memory operations from each processor one at a time and in program order, and (ii) ensure write operations execute atomically (i.e., as if there is a single copy of memory). The information conveyed by the labels in a PL1 program allows the system to relax some of these constraints while maintaining sequential consistency.

The system can exploit the distinction between competing and non-competing operations, and between competing read and competing write operations. Figure 3.5 illustrates the overlap and reordering that is possible among the operations from a single processor. Figure 3.5(a) shows a sample sequence of memory operations in program order. The operations shown in bold are competing operations. Each block of multiple operations depicts a sequence of non-competing operations between two competing ones. The numbers beside each block uniquely identify the block. Figure 3.5(b) shows the sufficient program orders that can be maintained to satisfy the PL1 model. Within each block of non-competing operations, reads and writes to different locations can be overlapped or reordered. The system can trivially distinguish between competing read and competing write operations to allow extra overlap between competing and non-competing operations. A competing read is only ordered with respect to operations that follow it in program order, while a competing write is only ordered with respect to operations that precede it in program order. This is analogous to the distinction between acquire and release operations in the release consistency model (see Section 2.4 of the previous chapter), and arises from the fact that the interprocessor links in an ordering chain (Definition 3.1) are always from a competing write to a competing read. Finally, program order is maintained among competing operations. Regarding atomicity, non-competing writes are allowed to appear non-atomic.

exploit most of the above optimizations; competing reads and writes can be mapped to acquire and release operations, respectively, and non-competing operations can be simply mapped to ordinary data operations. Chapter 4 describes a slightly more aggressive set of system requirements (relative to RCsc) that still satisfies the PL1 model. Overall, the most important optimization is the ability to reorder memory operations in between competing operations, which can provide a substantial performance potential especially if competing operations are infrequent.

3.2.2

Properly-Labeled Model—Level Two (PL2)

The second programmer-centric model we consider requires extra information about memory operations to identify competing operations that are directly used for synchronizing non-competing operations. Below, we describe the formal categorization of operations and the types of optimizations that are enabled by this extra information.

Categorization of Shared-Memory Operations for PL2

This section extends the categorization of memory operations to identify the subset of competing operations that are used to order non-competing operations through ordering chains. We refer to such operations as synchronization (abbreviated to sync) operations and the remaining competing operations are referred to as non-synchronization (or non-sync) operations.

Consider the program segment in Figure 3.4(b) (from the previous section) that shows two processors accessing memory locations within critical sections implemented using test-and-set operations. As we discussed in the previous section, the operations to locations A and B are non-competing because in every SC execution, there is an ordering chain between conflicting pairs of operations to these locations. Therefore, the read and write of the test-and-set and the write to unset the lock are the only competing operations in the program. By considering SC executions of this program, it becomes apparent that while the write to unset the lock and the read of the test-and-set are required to form ordering chains among conflicting operations to locations A and B, the write of the test-and-set is not part of the ordering chains. Intuitively, the write to unset the lock acts as a release operation and informs the other processor that operations that appear before it in program order have completed. Similarly, the read of the test-and-set acts an acquire operation which, in conjunction with the while loop, delays future operations that follow it in program order until a release is done by another processor. In contrast, the write of the test-and-set is simply used to ensure mutual exclusion and does not function as either an acquire or a release. Therefore, we categorize the read of the test-and-set and the write to unset the lock as synchronization operations and the write of the test-and-set as a non-synchronization operation.

Figure 3.6 shows the categorization of shared-memory operations for the PL2 memory model. Given this categorization, the valid labels for memory operations (i.e., leaves of the categorization tree) are sync, non-sync, and non-competing. As discussed above, read synchronization operations function as an acquire, while write synchronization operations function as a release. This extra distinction between read and write synchronization operations will also be used to allow further optimization, but is not shown as explicit labels since the distinction between reads and writes is trivial and automatic. The conservative labels are shown in bold in Figure 3.6. For example, operations that are non-competing or non-sync can conservatively be

sync