A MBIENTES DE FORMACIÓN

Parasitic transistors are formed everywhere on a silicon die wherever a conductor appears above and between the junction regions of different transistors. If the electrical potential on a conductor should approach the threshold voltage of a parasitic transistor underneath it, undesired leakage currents may flow between transistors that are intended to be unconnected. In order to prevent this, extra processing is performed to ensure that these parasitic transistors can not conduct appreciable current. Two popular methods to isolate transistors are local oxidation of the silicon (LOCOS) and shallow-trench isolation (STI).

p n

Fig. 2.5 The cross section of the wafer after the oxide definition (OD) regions are patterned.

n well

SiO₂ p^– Si₃N₄

Local Oxidation of Silicon (LOCOS)

LOCOS processing involves the implantation of additional dopants (filed-implants) between transistors to ensure any parasitic transistors have a very large threshold voltage, followed by the creation of very thick layers of SiO₂ (field-oxide) above the field-implants.

First, the field-implants are introduced under where the field-oxide will be grown. For example, boron is implanted under the field-oxide everywhere except in the well regions. This implant guarantees that the silicon under the field-oxide will never invert (or become ) when a conductor over the field-oxide has a large voltage.

For the field-oxide in the well regions, where -channel transistors will eventually reside, an -type implant such as arsenic (As) could be used. Often, it is not necessary to include field-implants under the field-oxide of the well regions because the heavier doping of the well (compared to that of the substrate) normally guarantees that the silicon will never invert under the field-oxide in these regions.

When implanting the field-implants in the substrate regions, it is necessary to first cover the wells with a protective photoresist, PR₃, so the -well regions do not receive the implant. This can be done using the same mask, M₁, that was originally used for implanting the wells, but now a positive photoresist is used. This positive photoresist remains where the mask is opaque (i.e., dark), which corresponds to the well regions.

After the exposed photoresist has been dissolved, we now have the cross section shown in Fig. 2.6. Notice that at this step, all the active regions, where eventually the transistors will reside, are protected from the field implants by the Si₃N₄ and SiO₂. Additionally, the complete well regions are also protected by PR₃. The field-implant will be a high-energy field-implant with a fairly high doping level. Before the field-oxide is grown, PR₃ is removed, but the silicon-nitride–silicon-dioxide sandwich is left.

The next step is to grow the field-oxide, SiO₂. There are two different ways that SiO₂ can be grown. In a wet process, water vapor is introduced over the surface at a moderately high temperature. The water vapor diffuses into the silicon and, after some intermediate steps, reacts according to the formula

(2.1) In a dry process, oxygen is introduced over the wafer, normally at a slightly higher temperature than that used in the wet process, and reacts according to the formula

(2.2) n

n

p n

n p

n

Fig. 2.6 The cross section when the field-implants are being formed in a LOCOS process.

n well

SiO₂ p^– Si₃N₄

PR₃

Field-implants Boron ions Si+2H2O→SiO₂+2H2

Si+O2→SiO2

Since both of these processes occur at high temperatures, around 800 to 1200 °C, the oxide that results is some-times called a thermal oxide.

The field oxide does not grow wherever CVD-deposited Si₃N₄ remains, because the Si₃N₄ is relatively inert to both water and oxygen. Wherever the process does occur, the volume increases because oxygen atoms have been added. Specifically, SiO₂ takes up approximately 2.2 times the volume of the original silicon. This increase will cause the SiO₂ to extend approximately 45 percent into, and 55 percent above, what previously was the surface of the silicon. The resulting cross section is shown in Fig. 2.7. Note that in our example process, the field-oxide in the substrate region has field-implants under it, whereas the field-oxide in the wells does not.

When growing thermal SiO₂, the wet process is faster because H₂O diffuses faster in silicon than O₂ does, but the dry process results in denser, higher-quality SiO₂ that is less porous. Sometimes, growing the field-oxide starts with a dry process, changes to a wet process, and finishes with a dry process. When thin layers of SiO₂ are grown, as the next section describes, usually only a dry process is used.

LOCOS is the preferred method for transistor isolation when minimum feature sizes exceed 0.25 μm. At smaller feature sizes the rounded corners of the field-oxide take up too much space and improved isolation pro-cessing is required.

Shallow-Trench Isolation (STI)

A STI process involves etching trenches into the silicon substrate between the active regions and filling the trenches with oxide. As with the field-oxide in a LOCOS process, the trench locations are defined by a Si₃N₄ layer.

Filling the trenches is a two-step process: first, the trenches are lined with a thin SiO₂ layer that is thermally grown; then additional oxide is deposited over the entire wafer, filling the trenches and leaving behind a very uneven surface. Finally, the top surface is polished to pla-narize it for further processing. These steps are performed at the start of the process flow, prior to well definition. An example wafer cross-section when STI is used in place of LOCOS is illustrated in Fig. 2.8. STI provides good isola-tion between transistors even when very closely spaced and is currently in wide use. However, it requires more Fig. 2.7 The cross section after the field-oxide has been grown in a LOCOS process.

Si₃N₄ SiO₂ Field-oxide

p⁺ field-implants n well

p^–

Si₃N₄ SiO₂

p^– n well

Fig. 2.8 The resulting wafer cross section when shallow-trench isolation (STI) is used between transistors.

steps than LOCOS and is therefore more expensive. Moreover, the creation and filling of the trenches places a strain on the silicon wafer’s lattice structure, which impacts the electrical characteristics of nearby transistors.