1. wor net is synthesizable.
Note: When coding for synthesis, the most commonly used type of declara-tion for net is wire. Net types tri, wand, and wor are synthesizable but not advis-able for use in synthesizadvis-able Verilog code. Net types trior, triand, trireg, tri1, and tri0 are not synthesizable.
In Verilog, each net or reg can have one of four values:
1 – represents logical 1 0 – represents logical 0 X – represents don’t care state Z – represents high impedance
INTRODUCTION TO BASIC VERILOG CONCEPTS 23
For nets with conditions of multiple drivers driving them, each driver having the possibility of driving any one of four values stated, what value would the net be at?
Assume net C is driven by two drivers, A and B. Both drivers can each drive any one of the four values of 1, 0, X, or Z, thereby allowing a possible com-bination of 16 conditions on the drivers. The final value on net C due to the 16 different driving conditions would depend on the net type that has been declared on net C.
1. tri Referring to Table 3.1, if driver A is driving a value of logic 0 and driver B is driving a value of logic 1, net C, which is declared as a tri net type, will have a value of X. Note: Net type wire has the same value as the net type tri for multiple drivers driving the net.
2. trior Referring to Table 3.2, if driver A or B is driving a value of logic 1, net C, which is declared as a trior net type, will have a value of 1.
3. triand Referring to Table 3.3, if driver A or B is driving a value of logic 0, net C, which is declared as a triand net type, will have a value of 0.
4. trireg Referring to Table 3.4, if drivers A and B are tristated, net C, which is declared as a trireg net type, will hold its previous value.
5. tri1 Referring to Table 3.5, if drivers A and B are tristated, net C which is declared as a tri1 net type, will have a value of 1.
TABLE 3.1. Table indicating value on net C (net type tri) for different net values on drivers A and B
tri A
1 0 Z X
1 1 X 1 X
0 X 0 0 X
B Z 1 0 Z X
X X X X X
TABLE 3.2. Table indicating value on net C (net type trior) for different net values on drivers A and B
Trior A
1 0 Z X
1 1 1 1 1
0 1 0 0 X
B Z 1 0 Z X
X 1 X X X
INTRODUCTION TO BASIC VERILOG CONCEPTS 25
TABLE 3.3. Table indicating value on net C (net type triand) for different net values on drivers A and B
Triand A
1 0 Z X
1 1 0 1 X
0 0 0 0 0
B Z 1 0 Z X
X X 0 X X
TABLE 3.4. Table indicating value on net C (net type trireg) for different net values on drivers A and B
Trireg A
1 0 Z X
1 1 X 1 X
0 X 0 0 X
B Z 1 0 Previous value X
X X X X X
TABLE 3.5. Table indicating value on net C (net type tri1) for different net values on drivers A and B
Tril A
1 0 Z X
1 1 X 1 X
0 X 0 0 X
B Z 1 0 1 X
X X X X X
6. tri0 Referring to Table 3.6, if drivers A and B are tristated, net C, which is declared as a tri0 net type, will have a value of 0.
7. wand Referring to Table 3.7, if drivers A or B are driving a value of logic 0, net C, which is declared as a wand net type, will have a value of 0.
8. wor Referring to Table 3.8, if drivers A or B are driving a value of logic 1, net C, which is declared as a wor net type, will have a value of 1.
3.1.5 Signal Strength
Section 3.1.3 has discussed in detail on the different types of net declarations as well as the usage of reg in Verilog. Each net type or reg can have the value
of 0, 1, X, or Z. The values of a net or reg, although limited to only these four values, can have eight different strengths (Table 3.9). The level of strength of a wire or reg is often used to resolve a situation when contention occurs.
Note: When coding for synthesis, strength levels are seldom used. This is because strength levels are used to resolve contentions within a logic circuit.
However, when coding for synthesis, it is a good coding practice to ensure that the Verilog code does not have contention. An example of a design that has contention is discussed in detail in Chapter 5.
Example 3.6 shows a simple Verilog code that assigns strength values to the output of a design.
TABLE 3.6. Table indicating value on net C (net type tri0) for different net values on drivers A and B
Tri0 A
1 0 Z X
1 1 X 1 X
0 X 0 0 X
B Z 1 0 0 X
X X X X X
TABLE 3.7. Table indicating value on net C (net type wand) for different net values on drivers A and B
Wand A
1 0 Z X
1 1 0 1 X
0 0 0 0 0
B Z 1 0 Z X
X X 0 X X
TABLE 3.8. Table indicating value on net C (net type wor) for different net values on drivers A and B
Wor A
1 0 Z X
1 1 1 1 1
0 1 0 0 X
B Z 1 0 Z X
X 1 X X X
Example 3.6 Verilog Code Using Strength Assignment
module example (inputA, inputB, inputC, outputA, outputB);
input inputA, inputB, inputC;
output outputA, outputB;
wire outputA, outputB;
and (strong1, weak0) and_gate_instance (outputA, inputA, inputB);
or (weak1, weak0) or_gate_instance (outputB, inputB, inputC);
endmodule
3.2 VERILOG GATE-LEVEL PRIMITIVES
Verilog allows coding to include gate-level primitives that can be instantiated in Verilog code. These primitives are built-in as part of Verilog coding and do not require any special setup.
Some of these primitives are synthesizable, whereas others are not. The fol-lowing lists the available gate-level primitives that can be used in Verilog coding:
VERILOG GATE-LEVEL PRIMITIVES 27
TABLE 3.9. Table showing different strength levels
Strength Type Level
Supply Strongest
Strong Pull Large Weak Medium Small
High impedance Weakest
During synthesis, synthesis tools would ignore the strength assignments. This example would synthesize to an AND gate and an OR gate.
1. pmos This primitive is used to represent a pmos transistor. It has two