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2.5.4.1 Pipelined Modified Booth Multiplier

A pipelined modified Booth multiplication is proposed to enhance the power per- formance ratio of 2’s complement multiplication. System architecture of the proposed scheme is catered for VLSI implementation. It is designed with the merit of low power consumption achieved by reducing the number of adder required. Only half of the adders is required as in traditional pipelined multiplier [54-56].

Modified Booth algorithm is widely used to implement multiplication in DSP systems and other applications. It provides high performance than other multiplication algorithms. However, the intrinsic architecture of the modified Booth algorithm does not have the regularity for VLSI pipeline implementation. For power reduction, re- ducing the supply voltage is widely used to improve the system power efficiency. It is most effective in pipelined data path comparing to other implementations such as par- allel data path and pipeline-parallel data path. It is desirable to employ pipelining in

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multiplication for DSP applications. Elrabaa et. al. proposed a sign extension scheme makes the multiplier array more regular for VLSI implementation. Nevertheless, it re- quires an n-bit adder at the last stage to sum all the terms from the multiplier array that impedes the system throughput of the multiplier. Besides, required 2’s comple- ment of multiplicand in Booth algorithm proscribes pipelining.

For reduction of power and supply voltage, pipelined data path is being widely used in DSP systems to enhance the system throughput. In the paper [58], we pro- posed a pipelined modified Booth multiplication to improve the system performance in terms of system throughput and power-performance ratio for low power low volt- age DSP applications.

2.5.4.2 Problems in computing 2’s complement number

Multiplying two numbers, X (multiplicand) and Y (multiplier), Booth algorithm en- codes the two’s complement multiplier, Y, to reduce the number of partial products to be added. The Radix - 4 modified Booth algorithm [57] divides the multiplier into overlapping groups of 3-bit encoded into {-2,-1,0,1, 2}. Each group is decoded to generate the partial product according the rule shown in Table 1.

The inherent problem in pipelining the modified Booth algorithm is the gen- eration of 2’s complement of the multiplicand. In conventional pipelined multiplier, a partial product is generated locally at each stage and added to the partial product from the previous stage with a single addition. However, in modified Booth algorithm, it may require multiple additions at each stage in order to generate the correct partial product that involves 2’s complement of the multiplicand (for the codes -1 and -2). In these cases, it requires the inversion of the multiplicand and addition of ‘1’ at the least significant bit for the code ’-1’, or the inversion of the multiplicand and left shift the multiplicand by one bit, and followed by the addition of ’10’ for the code ‘-2’. Such addition of ’1’ or ’10’ may lead to extra n additions in order to propagate the carry from the least significant bit to the most significant bit of the partial product. In other words, the 2’s complement of the multiplicand cannot be finished with one addition and one inversion operation.

2.5.4.3 Modified Booth Pipelined Multiplication

To pipeline the modified Booth multiplication [55-57], a partial product generation scheme is proposed to accommodate the 2’s complement “correction” bit/bits required

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for the code {-1, -2). Two extra bits are patched at the end of the least significant bit for any partial product. Value of these patched bits are “00”, “01” or “10” depending on the previous partial product encoded with the corresponding set of codes {2,1,0}, {-1}, and {-2}.

For 6x6 bits Radix-2 modified Booth multiplication, the original 9-bit partial product is extended to 11 bits: 9-bits partial product with Elrabaa algorithm, and 2-bit 2’s complement “correction”. Figure 2.21 shows the proposed partial product genera- tion. At any stage, it generates a partial product consists of the multiplicand for the codes (2, 1, 0) or its inversion for the codes (-1, -2}, and 2-bit 2’s complement “cor- rection”. The 2’s complement “correction” bits are passed to the next stage. At any stage, the first part of the partial product (the multiplicand or its inversion) and the 2’s complement “correction” bits from the previous partial product are added to the par- tial product. However, at any intermediate stage except the first stage, it involves an addition of four operands: sum and carry from previous stage (s2, c1), the carry from the second least significant bits from the addition of (s1, c0), and the patched “correc- tion” bit (Yi) indicated as the dashed objects in Figure 2.22. For proper addition, the traditional full adder cannot be used in this case.

To solve the problem, an encoding scheme is developed for the patched “cor- rection” bits, XiYi, at any intermediate stage. Values of these patched ”correction” bits are “00”, “01”, or “10” depending on the corresponding set of Booth codes {2,1,0}, {-1-, 2) of the partial product of the previous stage. Since it only involves a 2-bit addition of the second least significant bits (s1,c0), XiYi are recoded to ”0l”, “10” or “11” upon the result of the logic evaluation of “s1 AND c0’’ that can be achieved by a simple AND gate. In other words, a ‘0’ or ‘1’ is added to XiYi depending on the

carry from the addition of s1 and c0. The possible result of such operation is “00”, “01”,”00” or “11”. It never has the case needed to propagate a carry to the more sig- nificant bits resulted from this addition as the possible values of XiYi are ”00”,

“01”,or “10”.

At any intermediate stage, XiYi passed from the previous stage is recoded ac-

cording to the result of the evaluation of the carry from the second least significant bits (s1, c0) before adding to the sums and carries evaluated from the previous stage. In fact, it will not have a large overhead for the recoding scheme to penalize the sys- tem performance at any intermediate stages.

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Figure 2. 21: Partial product generation for 6x6 bit modified Booth multiplication

Figure 2. 22: Data flow of a 6 X 6 bit modified Booth multiplication with the partial Product generation scheme

2.5.4.4 Results and Conclusion

The simulation result multipliers using tree structure and pipelined booth multiplier is given bellow.

Power for tree multiplier is 0.667μW Max Pin Delay: 8.113 ns Power for Pipelined booth multiplier- 0.43μW Max Pin Delay: 7.431 ns

Improved power efficiency of pipelined booth multiplier compared to tree multiplier is about 35.25% and a speed improvement of 8.4% is obtained.