CHAPTER II – LITERATURE REVIEW
CHAPTER 3: METHODOLOGY
Following the idea suggested in [124], an interesting alternative could be utilized to read and write registers’ data of a particular region without affecting the rest of the device. As that work states, a property named RESET AFTER RECONFIG=TRUE [108] can be utilized with 7 series devices to implement partially reconfigurable modules in order to avoid the manual unprotection/protection actions. When implementing partial reconfigurable designs with this property in 7 series (for UltraScale devices is always enabled), the partial bitstream created by Vivado contains the commands to protect the rest of the device (including static and remaining partial regions), maintaining the actual partial region unprotected.
Hence, this property enables to protect a particular partial region in a straight-forward fashion. Nevertheless, as Figure 4.16 shows, this method can only un-protect (open padlock) a single partial region at once. As it can be observed, every downloaded partial bitstream unprotects the target reconfigurable module and protects (closed padlock) the rest of the device, even if the a partial re-configurable module has been previously unprotected. Thus, there is no way to unprotect more than one partial region in the same device.
FPGA
Figure 4.16: Effect of the RESET AFTER RECONFIG=TRUE property in FPGA protection.
With the aim of solving the issue of unprotecting more than a single partial re-gion in 7 series devices, a novel design flow has been developed in this work.
As a first step, two reconfigurable regions (PblockA and PblockB ) have been designed. In the implementation process only PblockA has been implemented with the RESET AFTER RECONFIG property. After that, both generated partial bitstreams have been analysed and compared. The comparison has shown re-markable differences in the content, making it difficult to identify any special bit or command word. However, after a further analysis, a special word in 51st position of the frame with a particular content (0xE00009BC) has been observed
through the partial bitstream. Afterwards, a new comparison has been performed to detect discrepancies in the 0xE00009BC special word. The comparison results indicate that only two 0xE00009BC words appear in the A partial bitstream and do not appear in the B partial bitstream. Hence, it has been initially as-sumed that these two words were the protection words for the B reconfigurable region. In this way, different tests has been carried out modifying the partial bitstream of PblockA, downloading it and performing physical tests. These tests have concluded that erasing one of both special words has an effective protect-ing/unprotecting effect of PblockB.
Using the obtained information from the test the procedure described in Figure 4.17 has been developed. It utilizes the RESET AFTER RECONFIG=TRUE property in combination with the edition of the partial bitstream, as a straightforward method to protect or unprotect as many as desired partially reconfigurable mod-ules. This edition only requires to erase or to add the proper 0xE00009BC special word of the previously generated partial bitstream.
Once the partial regions have been unprotected, the content of the registers of the unprotected regions can be easy read and written by using the GCAPTURE and the GRESTORE, respectively without affecting the protected regions. When using the RESET AFTER RECONFIG=TRUE property it is advisable to also utilize the SNAPPING MODE constraint, which automatically creates legal reconfigurable blocks. This method, combined with a proper bitstream processing, also enables to modify data of registers, for instance for copying the content from one register to another.
The proposed method has a number of advantages and drawbacks that should be taken into account in order to choose the most adequate solution for each design. The most remarkable benefit of this alternative is that it is relatively fast, especially when capturing and restoring the context, because both GCAPTURE and GRESTORE operations are not time consuming processes. Thus, the time requirements are related to the time needed by the GSR signal to spread across the partial reconfigurable circuit, which is design dependant. In addition, this approach does not demand any additional element, neither external memories nor logical resources.
The most relevant drawback of this approach is the need of implementing par-tially reconfigurable blocks. In fact, when using the RESET AFTER RECONFIG=TRUE property, the partially reconfigurable module’s height must align to clock region boundaries, which means occupying an entire column of resources (there is no block width restriction). Depending on the design, this could limit the avail-able resources for other purposes. It is interesting to mention that in UltraScale devices there is no height requirement, since the RESET AFTER RECONFIG=TRUE
VHDL design in Vivado (Erase 0xE00009BC )
Edited
Figure 4.17: Approach to unprotect several regions in 7 series devices based on the RESET AFTER RECONFIG property.
property is always enabled. Moreover, if the XADC component is used, its inter-face cannot respond during the partial reconfiguration period, blocking its access.
Another remarkable disadvantage of the use of the RESET AFTER RECONFIG=TRUE property is that, since the partial bitstream created contains the commands to protect the rest of the device and to unprotect the partial region, the size of the bitstream significantly increases.
Another important limitation when using approaches that utilize partial recon-figuration schemes is that the maximum achievable operating frequency of the design can be reduced. Although two identical designs, one static and another reconfigurable, can be logically exactly equal from an RTL description point of view, the way both are synthesized and implemented is significantly different.
The partial reconfiguration flow demands to synthesize each reconfigurable mod-ule out of context, which limits cross-boundary optimizations. The reason for this is to guarantee that logical interfaces between static and reconfigurable partitions remain fixed. During the implementation, the Pblocks are required to physically divide the static and reconfigurable partitions. This implies layout requirements that also restrict the optimization of the placement process.