LA MUESTRA FINAL

There are several types of commercial vertical NPN SiGe HBT device structures. SiGe processes use advanced fabrication technologies to optimize performance characteristics. These process technologies were developed to maximize gain and frequency response of Si bipolar devices. The fabrication technologies focus on two independent areas of improvement: the intrinsic transistor performance and the reduction of parasitics inherent to a device structure.

The intrinsic transistor performance is optimized by the transistor’s doping profile and layer thicknesses. The development of in-situ doped epitaxial layers allows extremely accurate control of doping concentration and layer growth rate. This technology greatly improves the ability to tailor doping profiles and minimize region thicknesses [19].

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The second area of focus that fabrication techniques address is the minimization of parasitic resistance and capacitance within the intrinsic and extrinsic regions of the transistor. Doped polysilicon fabrication techniques allow self-alignment, thereby reducing contact spacing and area, as well as minimizing extrinsic contact resistances [11]. Shallow trench oxide isolation and deep trench poly filled isolation also reduce spacing rules and minimize area. The parasitic resistance and capacitance of each region is process specific and dependent upon the physical structure. High frequency analog and digital circuit designs require bipolar device structures to have minimum parasitic resistances and capacitances.

The intrinsic Si bipolar device has fundamental performance limits due to the relationship between doping concentrations and region thicknesses. Changes of either will improve the performance of one electrical characteristic, but unfortunately will begin to degrade another. The intrinsic transistor cross section of Figure 2.1 indicates the charge carrier concentration and layer thickness of each region, which relate to the electrical characteristics defined by the Si process design equations below.

Figure 2.1 Charge carrier concentration across an intrinsic cross section. Uniform doping was used and not drawn to scale [20].

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The relationship between electrical performance and process technology features of doping concentrations, diffusivity, and region thickness are summarized in Equations (2.1) thru (2.8) [11].

The Si NPN bipolar process Equations (2.1), (2.2) and (2.3) define DC currents and current gain of a heavily doped base with base bandgap narrowing included:

(2.1)

(2.2)

(2.3)

q Magnitude of electron charge, ( C ) k Boltzmann constant (eV/K)

T Device temperature (K) WB Intrinsic base width (nm) WE Neutral emitter width (nm) AE Active emitter area (um2)

ni0 Intrinsic concentration of undoped Si (cm-3) NdE Electron donor concentration in the emitter (cm-3₎ DpE Diffusion coefficient of holes in the emitter (cm2/s) NaB Hole acceptor concentration in the neutral base (cm-3) DnB Diffusion coefficient of electrons in the base (cm2/s) ΔEgb Bandgap narrowing due to heavy doping in the base (cm-3₎

The frequency response of the device is defined by cutoff frequency, fT, and is dependent upon the collector current, IC. For bipolar devices, fT is typically defined as:

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(2.4)

The depletion junction capacitances are defined by CJE and CJC. The forward transit time, τF, is the sum of the times required to travel through each region of the intrinsic transistor. The travel time needed for excess charge to pass through each region is defined as: , emitter transit time for the emitter region, , base transit time of the neutral base region, and , collector transit time for the collector space charge regions. The total transit time for a Si bipolar device is therefore described by the following equations:

(2.5)

(2.6)

(2.7)

(2.8)

QB Charge of the intrinsic base region QE Charge of the emitter region

QC Charge of the base-collector depletion region

Base-collector saturation drift velocity due high electric field (cm/s) WC Base-collector depletion region width (nm)

For a Si device the typical forward charge transit times of each region, are defined in the Equations (2.6), (2.7) and (2.8). In advanced Si devices the base transit time is assumed to have a non-uniform base doping from emitter to collector interfaces in order to maximize the

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accelerating built-in field. The tailoring of the base doping profile allows the denominator factor of to range from 2.5 to 4. The denominator factor of 4 reflects precision in-situ doping of a non-uniform base profile to minimize base transit time [11].

Advanced Si devices have a thin intrinsic basewidth and are heavily doped. This combination yields the highest cutoff frequency and maximum operating voltage range without decreasing DC current gain, βDC. Reducing the basewidth will decrease the base transit time, thereby increasing cutoff frequency. However, punchthrough of the collector to emitter regions occurs if the base region is too thin. Heavily doping the intrinsic base region prevents punchthrough. The drawback to a very high base doping concentration is that βDC decreases. Therefore, Si processing technologies have taken Si intrinsic doping and region thickness to the basic limits of Si material. The fT and βDC relationships discussed above are summarized in Table 2.1. [11]

Performance

Enhancement

Process

Technique

Advantage

Disadvantage

basewidth

τB decrease breakdown voltage decreases due to punchthrough punchthrough voltage increases increase base doping depletion regions decrease βDC decreases RB(total) decreases increase base doping RB(intrinsic) decreases βDC decreases fT increases increase collector doping

τC decreases breakdown voltage decreases

Table 2.1 Performance enhancements of intrinsic Si transistors

Polysilicon fabrication enables the use of self-aligned fabrication techniques that reduce layout spacing dimensions. A double polysilicon process of poly emitter and polysilicon extrinsic base minimizes the spacing rules between emitter and extrinsic base regions [11]. The overall size of the regions can be reduced, thereby reducing junction areas and peripheries which

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reduce components, CJE and CJC [21]. Polysilicon emitters can be very heavily doped to reduce emitter resistance, RE. Extrinsic polysilicon base regions are also heavily doped to minimize extrinsic base resistance. The extrinsic polysilicon base regions are grown over shallow trench isolation to reduce parasitic base-collector capacitance.

In-situ doped epitaxially grown layers allow optimum control of doping and layer thickness. Very thin intrinsic base layers of less than 100 nm are possible and can be heavily doped with precise control. A lightly doped N- collector region is fabricated by epitaxially growing an N- Si layer of a few hundred nm in thickness on top of the heavily doped N+ buried collector layer [19].

The following table summarizes the benefits of Si and SiGe advanced process technologies discussed above.

Process Feature Enhancement

Frequency Response Component Improved

polysilicon-emitter minimizes peripheral base- emitter capacitance

CJE decreased polysilicon extrinsic base reduces base-collector

capacitance

CJC decreased thin, in situ P+ _epitaxial

grown base

minimizes basewidth,

increases intrinsic base doping

τF decreased RB decreased epitaxial grown collector

region

lightly-doped N- region reduces capacitance at B-C interface

CJC decreased buried N+ collector N+ with surface collector

contact thru deep N+ plug

RC decreased shallow trench oxide reduces extrinsic base-collector

capacitance

CJC decreased deep trench lateral isolation between

devices CJS decreased

substrate surface contact by deep P+ plug to the P- substrate

device isolation RSubstrate decreased

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Shallow trench oxide is used for lateral isolation. It greatly reduces the parasitic base- collector capacitance by removing the P-N junction between the extrinsic base and active collector region. Deep trench isolation greatly reduces layout dimensions over junction isolation methods thereby reducing area and periphery capacitances.