EL NIÑO CONSEGUIDO NO CONSEGUIDO

Figure 14.1 shows a typical clocking network with multiple clock buffers. The waveforms show skew at various points in the clock tree. The skew comes from timing uncertainties in the buffers, as well as board-level effects. In some cases, the skew may not be important, but in other designs it must be carefully controlled. If the two devices on the left communicate with one another, it might be important to control the clock skew at points C’ and D’. Controlling skew traditionally means minimizing it, however, there are some situations where intentionally skewing the clocks is required.

Figure 14.1 Skew Example

To minimize skew, the number of cascaded devices should be limited. This means that one clock buffer used for fanout should not be followed by another fanout buffer if the goal is to minimize skew among all of the resulting clock signals. This is because each additional clock device in series adds more potential skew. While this is true in general, it is also important to note that skew specifications are not the same for every device, and there may be cases where two very-low-skew buffers in series can give less skew overall than a single high-skew buffer. If skew is important only across the outputs of a single device, this is not an issue. Note, however, that jitter can accumulate with cascaded PLL-based zero-delay clock buffers (see Chapter 8, Cascading PLLs).

tSKEW Clk D' Buffer D C' D' B' A' C Clk C' Clk B' Clk A' Buffer Clock B A

Given the clock buffer configuration in Figure 14.2 where buffer B is a zero-delay device, we see that skew across clocks 1, 2, 4, 5, 6, and 7 will be greater than the skew across clocks 4, 5, 6, and 7.

Figure 14.2 Cascaded Buffers

Similarly, a single buffer has less skew than two buffers in parallel. This is primarily due to process variation from device to device. While multiple buffers should be avoided wherever possible, it is not always realistic and does not need to be the overriding consideration. The data sheet values to consider are output-to-output skew and device-to-device skew, which are discussed later in this chapter. Note that device-to-device skew is not affected by the number of devices, so three buffers in parallel will have the same overall skew as two. Once again, two (or more) low-skew buffers may have less overall skew than a single high-skew buffer, so clock distribution design can be aided by an early examination of the pertinent clock buffer specifications.

If several clocks of a given frequency are needed but only some of them have tight skew requirements, then those clock signals should be buffered together by the same low-skew device(s), where possible.

Driving multiple loads from a single output buffer might appear to be a good method for controlling skew by reducing buffer count, but it is generally discouraged for signal integrity reasons. (For a guideline on driving multiple loads, see the Multiple Loads section in Chapter 7, Clock Termination.) While it is sometimes convenient for a single output to drive two loads, the preferred practice is to drive all clocks as single-loaded, point-to-point trace.

Another issue arises when distributing clocks that contain spread spectrum for EMI reduction (see Chapter 9, Electromagnetic Interference for more information on spread spectrum). Because spread-spectrum devices modulate the output frequency, precautions must be taken to maintain minimal skew. First, there must be a single source for the spread- spectrum clock. Multiple spread-spectrum clocks generated from the same frequency will not be in phase due to the modulation. And second, downstream zero-delay clock buffers must be “spread aware”, otherwise excessive jitter will be generated.

Layout

Clock skew should also be considered during board floorplanning. There are many factors to consider when determining where to position components on a board, but skew should

1 4 - 3 Clock Buffer B 4 5 6 7 Clock Buffer A 1 2 3 Source Clock

be given appropriate attention. The designer should determine which devices belong to each clock domain and rank the relative skew importance of each appropriately. The components and clock source of skew-critical domains should be placed as close together as possible. If the relative clock trace length requirements are known, locate the clock source and buffer(s) so the traces are short and additional trace delay is not needed. Short traces minimize skew uncertainty and maximize signal integrity.

Of course, there are times when such goals are not achievable. In such cases, the goal is to maintain signal integrity and balance the distribution network with no more buffering than is necessary. For example, a clock source may be located on one side of the board while the destination devices must be placed on the opposite side. By locating the clock buffer near the destination devices, a single clock trace to the buffer need only traverse the length of the board instead of multiple copies of the clock. Another situation that often occurs is that the destination devices cannot be located near one another. In the case of non- adjacent destination devices, placing the fanout buffer midway between the destination devices usually provides the best results.