OBSERVACIÓNES DE LOS EFECTOS EN LAS CUATRO ESPECIES DE ANUROS FRENTE A CAMBIOS DE pH

The security architecture of an information system is fundamental to enforcing the organization’s information security policy. Therefore, it is important for security professionals to understand the underlying computer architectures, protection mechanisms, distributed environment security issues, and formal models that provide the framework for the security policy. In addition, professionals should have knowledge of the assurance evaluation, certification and accreditation guidelines, and standards. The following topics are addressed in this chapter:

§Computer organization §Hardware components §Software/firmware components §Open systems §Distributed systems §Protection mechanisms §Evaluation criteria

§Certification and accreditation

§Formal security models

§Confidentiality models

§Integrity models

§Information flow models Computer Architecture

The term computer architecture refers to the organization of the fundamental elements comprising the computer. From another perspective, it refers to the view that a programmer has of the computing system when viewed through its instruction set. The main hardware components of a digital computer are the Central Processing Unit (CPU), memory, and input/output devices. A basic CPU of a general-purpose digital computer is comprised of an Arithmetic Logic Unit (ALU), control logic, one or more accumulators, multiple general-purpose registers, an instruction register, a program counter, and some on-chip local memory. The ALU performs arithmetic and logical operations on the binary words of the computer.

These computer elements are interconnected by a group of conductors called a bus. The bus runs in a common plane with the different computer elements connected to the bus. A bus can be organized into subunits, such as the address bus, the data bus, and the control bus. A diagram of the organization of a bus is shown in Figure 5.1.

Figure 5.1: A computer bus. Memory

Several types of memory are used in digital computer systems. The principal types of memory and their definitions are as follows:

Cache memory. A relatively small amount (when compared to primary memory) of very high speed RAM, which holds the instructions and data from primary memory that have a high probability of being accessed during the currently executing portion of a program. Cache logic attempts to predict which instructions and data in main memory will be used by a currently executing program. It then moves these items to the higher speed cache in anticipation of the CPU requiring these programs and data. Properly designed caches can significantly reduce the apparent main memory access time and thus, increase the speed of program execution.

Random Access Memory (RAM). Memory where locations can be directly addressed and the data that is stored can be altered. RAM is volatile due to the fact that the data is lost if power is removed from the system. DynamicRAM (DRAM) stores the information on parasitic capacitance that decays over time. Therefore, the data on each RAM bit must be periodically refreshed. Refreshing is accomplished by reading and rewriting each bit every few milliseconds. Conversely, static RAM (SRAM) uses latches to store the bits and does not need to be refreshed. Both types of RAM, however, are volatile. Programmable Logic Device (PLD). An integrated circuit with connections or internal logic gates that can be changed through a programming process. Examples of a PLD are a Read Only Memory (ROM), a Programmable Array Logic (PAL) device, the

Complex Programmable Logic Device (CPLD), and the Field Programmable Gate Array

(FPGA.) Programming of these devices is accomplished by blowing fuse connections

on the chip, using an antifuse that makes a connection when a high voltage is applied to the junction, through mask programming when a chip is fabricated, and by using SRAM latches to turn an Metal Oxide Semiconductor (MOS ) transistor on or off. This last technology is volatile because the power to the chip must be maintained for the chip to operate.

Read Only Memory (ROM). Non-volatile storage where locations can be directly addressed. In a basic ROM implementation, data cannot be altered dynamically. Non-

volatile storage retains its information even when it loses power. Some ROMs are implemented with one -way fusible links and their contents cannot be altered. Other types of ROMs — such as Erasable Programmable Read Only Memories (EPROMs), Electrically Alterable Read Only Memories (EAROMs), Electrically Erasable Programmable Read Only Memories (EEPROMs), Flash memories, and their derivatives — can be altered by various means, but only at a relatively slow rate when compared to normal computer system reads and writes. ROMs are used to hold programs and data that should normally not be changed or are changed infrequently. Programs stored on these types of devices are referred to as firmware.

Real or primary memory. The memory directly addressable by the CPU and used for the storage of instructions and data associated with the program that is being executed. This memory is usually high-speed, Random Access Memory (RAM).

Secondary memory. This type of memory is a slower memory (such as magnetic disks) that provides non-volatile storage.

Sequential memory. Memory from which information must be obtained by sequentially searching from the beginning rather than directly accessing the location. A good example of a sequential memory access is reading information from a magnetic tape.

Virtual memory. This type of memory uses secondary memory in conjunction with primary memory to present a CPU with a larger, apparent address space of the real memory locations.

A typical memory hierarchy is shown in Figure 5.2 .

Figure 5.2: A computer memory hierarchy.

There are a number of ways that a CPU can address memory. These options provide flexibility and efficiency when programming different types of applications, such as searching through a table or processing a list of data items. The following are some of the commonly used addressing modes:

§ Register addressing. Addressing the registers within a CPU or other

special purpose registers that are designated in the primary memory.

§ Direct addressing. Addressing a portion of primary memory by

specifying the actual address of the memory location. The memory addresses are usually limited to the memory page that is being executed or page zero.

§ Absolute addressing. Addressing all of the primary memory space.

§ Indexed addressing. Developing a memory address by adding the

contents of the address defined in the program’s instruction to that of an

index register. The computed, effective address is used to access the

desired memory location. Thus, if an index register is incremented or decremented, a range of memory locations can be accessed.

§ Implied addressing. Used when operations that are internal to the processor must be performed such as clearing a carry bit that was set as a result of an arithmetic operation. Because the operation is being performed on an internal register that is specified within the instruction itself, there is no need to provide an address.

§ Indirect addressing. Addressing where the address location that is

specified in the program instruction contains the address of the final desired location

An associated definition is the definition of memory protection.

Memory protection. Means to prevent one program from accessing and modifying the memory space contents that belong to another program. Memory protection is implemented by the operating system or by hardware mechanisms.

Instruction Execution Cycle

A basic machine cycle consists of two phases, fetch and execute. In the fetch phase, the CPU presents the address of the instruction to memory, and it retrieves the instruction located at that address. Then, during the execute phase, the instruction is decoded and executed. This cycle is controlled by and synchronized with the CPU clock signals. Because of the need to refresh dynamic RAM, multiple clock signals known as multi-phase clock signals are needed. Static RAM does not require refreshing and uses single-phase clock signals. In addition, some instructions may require more than one machine cycle to execute, depending on their complexity. A typical machine cycle showing a single-phase clock is shown in Figure 5.3. Note that in this example, four clock periods are required to execute a single instruction.

Figure 5.3: A typical machine cycle.

A computer can be in a number of different states during its operation. When a computer is executing instructions, this is sometimes called the run or operating state. When application programs are being executed, the machine is in the application or

problem state because it is hopefully calculating the solution to a problem. For security purposes, users are permitted to access only a subset of the total instruction set that is available on the computer in this state. This subset is known as the non-privileged

individual who authorized to use those instructions. A computer is in a supervisory state when it is executing these privileged instructions. The computer can be in a wait state, for example, if it is accessing a slow memory relative to the instruction cycle time, which causes it to extend the cycle.

After examining a basic machine cycle, it is obvious that there are opportunities for enhancing the speed of retrieving and executing instructions. Some of these methods include overlapping the fetch and execute cycles, exploiting opportunities for parallelism, anticipating instructions that will be executed later, fetching and decoding instructions in advance, and so on. Modern computer design incorporates these methods and their key approaches are provided in the following definitions:

Pipelining. Increases the performance in a computer by overlapping the steps of different instructions. For example, if the instruction cycle is divided into three parts — fetch, decode, and execute — instructions can be overlapped as shown in Figure 5.4 to increase the execution speed of the instructions.

Figure 5.4: Instruction pipelining.

Complex-Instruction-Set-Computer (CISC). Uses instructions that perform many operations per instruction. This concept was based on that fact that in earlier technologies, the instruction fetch was the longest part of the cycle. Therefore, by packing the instructions with several operations, the number of fetches could be reduced.

Reduced-Instruction-Set-Computer (RISC). Uses instructions that are simpler and require fewer clock cycles to execute. This approach was a result of the increase in the speed of memories and other processor components, which enabled the fetch part of the instruction cycle to be no longer than any other portion of the cycle. In fact, performance was limited by the decoding and execution times of the instruction cycle. Scalar Processor. A processor that executes one instruction at a time.

Superscalar Processor. A processor that enables concurrent execution of multiple instructions in the same pipeline stage as well as in different pipeline stages.

Very-Long Instruction-Word Processor (VLIW). A processor in which a single instruction specifies more than one concurrent operation. For example, the instruction may specify and concurrently execute two operations in one instruction. VLIW processing is illustrated in Figure 5.5.

Figure 5.5: Very-Long Instruction Word (VLIW) processing.

Multiprogramming. Executes two or more programs simultaneously on a single processor (CPU) by alternating execution among the programs.

Multitasking. Executes two or more subprograms or tasks at the same time on a single processor (CPU) by alternating execution among the tasks.

Multiprocessing. Executes two or more programs at the same time on multiple processors.

Input/Output Structures

A processor communicates with outside devices through interface devices called input/output (I/O) interface adapters. In many cases, these adapters are complex devices that provide data buffering, and timing and interrupt controls. Adapters have addresses on the computer bus and are selected by the computer instructions. If an adapter is given an address in the memory space and, thus, takes up a specific memory address, this design is known as memory-mapped I/O. The advantage of this approach is that a CPU sees no difference in instructions for the I/O adapter and any other memory location. Therefore, all the computer instructions that are associated with memory can be used for the I/O device. On the other hand, in isolated I/O, a special signal on the bus indicates that an I/O operation is being executed. This signal distinguishes an address for an I/O device from an addess to memory. The signal is generated as a result of the execution of a few, selected I/O instructions in the computer instruction’s set. The advantage of an isolated I/O is that its addresses do not use up any addresses that could be used for memory. The disadvantage is tha t the I/O data accesses and manipulations are limited to a small number of specific I/O instructions in the processor’s instruction set. Both memory-mapped and isolated I/Os are termed programmed I/Os.

In a programmed I/O, data transfers are a function of the speed of the instruction’s execution, which manipulates the data that goes through a CPU. A faster alternative is

direct memory access (DMA). With DMA, data is transferred directly to and from

memory without going through a CPU. DMA controllers accomplish this direct transfer in the time interval between the instruction executions. The data transfer rate in DMA is limited primarily by the memory cycle time. The path of the data transfer between memory and a peripheral device is sometimes referred to as a channel.

Another alternative to moving data into and out of a computer is through the use of

interrupts. In interrupt processing, an external signal interrupts the normal program flow and requests service. The service may consist of reading data or responding to an emergency situation. Adapters provide the interface for handling the interrupts and the means for establishing priorities among multiple interrupt requests. When a CPU

receives an interrupt request, it will save the current state of the information related to the program that is currently running, and it will then jump to another program that services the interrupt. When the interrupt service is completed, the CPU restores the state of the original program and continues processing. Multiple interrupts can be handled concurrently by nesting the interrupt service routines. Interrupts can be turned off or masked if a CPU is executing a high priority code and does not want to be delayed in its processing.

Software

The CPU of a computer is designed to support the execution of a set of instructions associated with that computer. This set consists of a variety of instructions such as ADD WITH CARRY, ROTATE BITS LEFT, MOVE DATA, and JUMP TO LOCATION X. Each instruction is represented as a binary code that the instruction decoder of the CPU is designed to recognize and execute. These instructions are referred to as

machine language instructions. The code of each machine language instruction is

associated with an English-like mnemonic to make it easier for people to work with the codes. This set of mnemonics for the computer’s basic instruction set is called its

assembly language, which is specific to that particular computer. Thus, there is a one- to-one correspondence of each assembly language instruction to each machine language instruction. For example, in a simple 8-bit instruction word computer, the binary code for the ADD WITH CARRY machine language instruction may be 10011101 and the corresponding mnemonic could be ADC. A programmer who is writing this code at the machine language level would write the code using mnemonics for each instruction. Then, the mnemonic code would be passed through another program called an assembler that would perform the one-to-one translation of the assembly language code to the machine language code. The code generated by the assembler running on the computer is called the object code and the original assembly code is called the source code. The assembler software can be resident on the computer being programmed and, thus is called a resident assembler. If the assembler is being run on another computer, the assembler is called a cross assembler. Cross assemblers can run on various types and models of computers. A disassembler

reverses the function of an assembler by translati ng machine language into assembly language.

If a group of assembly language statements are used to perform a specific function, they can be defined to the assembler with a name called a MACRO. Then, instead of writing the list of statements, the MACRO can be called, causing the assembler to insert the appropriate statements.

Because it is desirable to write software in higher level, English-like statements, high-

level or high-order languages are employed. In these languages, one statement usually

requires a number of machine language instructions for its implementation. Therefore, unlike assembly language, there is a one-to-many relationship of high-level language instructions to machine language instructions. Pascal, FORTRAN, BASIC, and Java are examples of high-level languages. High-level languages are converted to the appropriate machine languages instructions through either an interpreter or compiler

programs. An interpreter operates on each high-level language source statement individually and performs the indicated operation by executing a predefined sequence of machine language instructions. Thus, the instructions are executed immediately. Java and BASIC are examples of interpreted languages. In contrast, a compiler translates the entire software program into its corresponding machine language instructions. These instructions are then loaded in the computer’s memory and are executed as a program package. FORTRAN is an example of a compiled language. From a security standpoint, a compiled program is less desirable than an interpreted one because malicious code can be resident somewhere in the compiled code, and it is difficult to detect in a very large program.

High-level languages have been grouped into five generations, and they are labeled as a Generation Language (GL). The following is a list of these languages:

§ 1 GL. A computer’s machine language

§ 2 GL. An assembly language

§ 3 GL. FORTRAN, BASIC, PL/1, and C languages

§ 4 GL. NATURAL, FOCUS, and database query languages

§ 5 GL. Prolog, LISP, and other artificial intelligence languages that

process symbols or implement predicate logic

The program or set of programs that control the resources and operations of the computer is/are called an operating system (OS.) Operating systems perform process management, memory management, system file management, and I/O management. Windows 2000, Linux, and Unix are some examples of these operating systems.

An OS communicates with I/O systems through a controller. A controller is a device, which serves as an interface to the peripheral, and runs specialized software to manage communications with another device. For example, a disk controller is used to manage the information exchange and operation of a disk drive.