Obtención de cis-biciclo[3.3.0]octano-3,7-dionas

60%, which will eventually lead to inefficient communication systems which hinder the overall system performance.

As an alternative, this thesis proposed that on-FPGA communication bandwidth can be efficiently increased by exploiting the electrical properties in the underlying reconfigurable architecture, by means of wave-pipelining. Using an analogue wave intra-chip signalling scheme, throughput of interconnection can be increased up to 5.6 times. Evaluations of the wave-pipelining scheme in devices from the SPICE modeling and Xilinx Virtex-4 families are presented. These have demonstrated the implementation of testing circuits in real-world commercial FPGAs, as presented in Chapter 4.

Because of the increase in communication and system complexities, traffic for on-chip transporta-tion is difficult to predict at design time. Optimizatransporta-tion and synthesis of the communicatransporta-tion archi-tecture at design time may not be able to fully utilize the hardware resources to adapt to dynamic traffic. Therefore, by incorporating intelligent plasticity with “the-fly” optimization in the on-chip communication system will enable a substantial improvement in communication bandwidth and efficiency. A Dynamic Programming (DP)-network is introduced in Chapter 5 to enable real-time optimization for on-chip communication. The DP-network implements an optimization algo-rithm with a distributed architecture which enables the network-on-chip (NoC) to deliver optimal path planning for packet-routing. The network consolidates and adapt to the real-time traffic. It has been demonstrated that the DP network can improve the overall delay performance by diverting the traffic to avoid hot spots when compared to other static routing approaches. The DP-network provides an interesting alternative to enable adaptation to the network traffic and can potentially to be applied for fault-tolerant routing in NoC.

6.2 Future Work

The work in this thesis can be continued and extended in a variety of directions.

Firstly, the primary objective of the study presented in this thesis is the optimization of on-chip throughput or bandwidth performance. In particular, a signalling scheme adopting an analogue wave can substantially enhance throughput. However, as discussed in Chapter 4, numerous dy-namic noise sources and static skew can hamper the performance and may even create a

communi-cation fault. Similarly, other recently proposed novel aggressive signalling schemes also exhibit a potential vulnerability in dynamic errors. From a reliability perspective, this is also a critical issue to be investigated. Some steps in this direction have recently been taken by Teehan, Lemieux and Greenstreet in [TLG09].

Besides, with aggressive scaling, interconnects at nanometre-scale are increasingly vulnerable to manufacturing defects, process variability and lifetime degradation. The reduction of lithographic pattern width and separation has led to more defects. Gradual degradation and failure of intercon-nects in future technologies obligates pessimistic over-design. Interconnect reliability is further reduced by the nanoscale’s inherent random parametric behaviour. Reliable on-chip communica-tion is crucial. In the context of communicacommunica-tion-centric system design, Network-on-Chip (NoC) provides an effective solution with high level routing and reliable communication protocols for complex computer architectures. Faulty regions or paths can be avoided by using this on-chip dynamic routing network.

Three key directions have been identified that provide the fundamental basis for future research.

(i) Adaptation with “on-the-fly” optimization is a promising technique to implement reliable ser-vices within an unreliable environment, potentially avoiding the high cost of classical redundancy.

As demonstrated in Chapter 5, a DP-network with real-time resolution of the optimization problem can substantially enhance communication performance. Such an approach can be further extended to provide real-time control of power and reliability, and potentially enabling new functionalities.

Current methods tend to focus on design-time optimization that would limit the capability to tackle the sophisticated dynamic on-chip environment.

(ii) Asynchrony and clock domain decoupling have been proposed as a potential solution to the problems caused by variation, and continued scaling has forced asynchrony onto long links. As VLSI systems continue to scale, judicious system partitioning and integration with asynchrony can potentially enhance the reliability of communication systems.

(iii) Virtualization is an important technique in system design to reduce designer effort and im-proving designer efficiency. Currently this is not being explored at a level of abstraction (across the physical and data link layers) suitable for on-chip communication links. Virtualization can provide an alternative solution for reliable communication in on-chip links. This can be done by

6.2 Future Work 164

isolating the system designer from the imperfections of underlying technology and encapsulating the complexity of the underlying communication architectures.

In conclusion, while this thesis demonstrated significant progress in the investigation of bandwidth utilization and degradations (Chapter 3), intra-chip bandwidth optimization using analogue wave on-FPGA signalling (Chapter 4) and the novel DP-network for on-chip dynamic routing (Chapter 5), a wide variety of objectives, architectures and new technology adaptations will benefit from further study.

Appendix A

A Simple Approximation of Interconnections Length

A simple methodology to approximate interconnection length in communication link [MSCL07]

is presented. This approach provides a fast approximation with simple algebraic modelling for interconnection length and channel utilization.

A.1 Average Interconnections Length

Consider a typical communication link with (S) bits, the two placement constraint areas are (L) tiles apart. The placement area is (A), width (u) and length (v), thus A = uv, as shown in Fig. 3.3(a). Let the number of long wires at each channel be (W ), and the number of channels that are required to implement S bits communication link will be S/W . It is also assumed that a random placement of pins at the constrained region. This is a reasonable assumption, as the hierarchical placement assumption for random logics is not applicable for communication links.

Therefore, the average interconnections length R is then given by

R =





S/WX

k=1

W · R_k



 /S (A.1)