Obtención de los serrulatanos a gran escala.

A novel mixed-signal low power dual band WFGINT with wide frequency range is presented. It is based on a relaxation oscillator comprising a hysteresis Schmitt Trigger and an integrator timing network circuit along with FD using cascading multiple divide-by-two (f/2) circuits. Using an active gm-C integrator as relaxation timing network has the advantage that its gm can be controlled directly by the biasing current. Also, it can be implemented using small gm values to provide low frequency oscillation and optimize its parameters, including DC gain, output swing, linearity and other performance parameters. This type of WFGINT circuit is preferred for tuneable, low-

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power, low-cost, miniaturized single-chip design with high functionality. WFGINT circuit based OTAs can be designed to achieve a wide tuning range with practical area and power constraints. Low frequency oscillators (several kHz to < Hz) have distinctive design challenges [194],while having many interesting applications in biomedical and geophysical systems [195, 196]. Although many reported designs achieve low power consumption with a narrow frequency tuning range, many complex applications require a wide frequency tuning range, along with compensation for PVT fluctuations.

The WFGINT circuit in this research project is designed to oscillate with no input, generating a periodical low frequency square/triangular waveform signal, and maintaining infinite output. The WFGINT circuit toggles spontaneously between two quasi-stable states and , remaining in its quasi-stable state for a fixed interval of time, and then returns to its original stable state. No external trigger signal is required to yield the changes in the state; it is a free-running oscillator circuit. An internal trigger signal is characterized by the charging and discharging of a capacitor, producing the required internal trigger signal which drives the circuit to return to its original stable state. The component values of the gm-C integrator are designed and used to set the time constant for which the circuit remains in each state. Since gm of the integrator circuit can be controlled directly by the DC biasing current, tuning of the oscillation frequency of the WFGINT core with simple tuning circuitry can then be realized easily. It is a simple and compact structure, considered as a power-efficient and small chip area solution with low cost for the longer battery life biomedical device, compared with a number of other architectures.

As a general design requirement, and since the power dissipation of the designed digital circuit is dominated by the FD circuit which has an inherently power hungry nature, the low-power design goal of the FD circuit becomes the task of minimizing, while also remembering the precise functionality and identifying the trade- offs of such minimizations in terms of performance and area. The optimal FD architectures and size are dependent upon the particular D-FF topology and its operating condition. As previously mentioned (section 2.8.2), Master–Slave D-FF (TGMS) are more popular and simpler than other D-FF topologies; their advantages include small chip area occupation and low power dissipation, thus TGMS can be effectively implemented in power-efficient microchips. In practical designs and for dependable results, an appropriate sizing is required. Since the target design of this project is a

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portable device for biomedical applications, power consumption and chip area are the major concerns in this design. Hence, the FD circuit design with small chip area and low power consumption can be based on TGMS, with the advances of CMOS technology that enables scaling down of MOSFET transistors in their size, for use in a low-cost CMOS digital circuit. When targeting a compact and extra power-efficient realization with good performance contribution, it is valuable, at least to some extent, to design a simple and suitable circuit solution based technique. An appropriate technique used to reduce the overall power consumption in this research project is through selecting 130-nm CMOS technology, using low supply voltage and low frequency operations with minimum device size and account circuit design, can enhance the low power design for life time battery operated biomedical devices. The present movement in this work is to:

1. Scale down the circuit size by using an appropriate 130-nm CMOS technology, with appropriate increase in the performance of the device.

2. Realize a low frequencies timing network by implementing a first order gm-C integrator approach, utilizing a single stage OTA as an active building block, implemented with a low transistor account; only four transistors and one grounded capacitor to reduce supply voltage, power and chip area. Design a gm-C integrator with small gm and small MIM capacitor of only 10pF, to eliminate the need for large resistors and capacitor values, hence, implement the WFGINT circuit fully on chip, with a small silicon area; since a large capacitor is needed for low frequency WFG design, the size and cost of the implant are impacted considerably by these reasonably large capacitances. A prevailing advantage of gm-C technique is that its gm can be designed for low frequency applications and can also be controlled directly by the biasing current to provide a wide frequency tuning range.

3. Design an appropriate and novel frequency tuning technique using a hybrid tuning system composed of an analog model and a digital model, so a sufficiently wide frequency output range is obtained, to compensate for PVT variations and to cover the required application bandwidth.

a) Analog model, comprising a first order electronically adjustable gm-C integrator using a mathematical model to design its gm parameters to perform three tasks; (1) the timing network, (2) for low frequency design, and (3) for the electronically tuneable WFGINT circuit (band I), linearly controlled by the bias current of the gm-C

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integrator through a smart and simple tuning gate-voltage (V_tune) that is driven by a single NMOS current source, without requiring an extra complex and complicated circuit. A large frequency tuning range with good linearity of gm-C integrator can then be achieved with small power consumption, using a small DC drain biasing current and a small W/L ratio, to the frequency scale of the gm-C integrator. This is also promising to provide a sub-frequencies output signal.

b) Digital model, comprising a FD which provides biphasic square waveform signals with its complementary signal, for better driving the electrode from 16 selected channels for electro-medical devices.

4. Design the device sizes and biasing currents of the WFGINT (including resistors and the capacitor) as well as the FD circuit to meet certain design requirements, including low speed, low power, and large output swing with small silicon area. Principally, to minimize power and silicon area consumption of the WFGINT, low biasing currents and minimum size devices are used, while the digital model is designed to operate at lower power dissipation by using the “ratioed” technique, which scales down the value of W/L of each device. The silicon area of the CMOS logic gate is also scaled down by simply modifying the W of the NMOS and PMOS transistors, without degrading the performance of the logic circuit.

5. A simple current mirror configuration is used for the WFGINT to provide multiple bias current, so as to reduce power consumption and silicon area.