In this section, in an effort to evaluate the impact of the previously analyzed nanoscale variability sources on the global electrical properties of MOS capacitors, fully- processed devices with equal gate dielectrics than those studied with CAFM have been investigated with standard characterization techniques. In particular, the gate conduction
Rms value
350°C 800°C
3.6nm 5.3nm 3.6nm 5.3nm
and electric field at breakdown (EBD) of Al-gated MOS devices have been studied. To
avoid die-to-die variability, all the measured devices were on the same die.
a) Impact of nanoscale variability sources on the device level electrical
conduction variability of MOS capacitors
The impact of the nanoscale variability sources on the gate electrical conduction of fully processed MOS devices is analyzed in this section. Fig. 3.7 shows some examples of I- V curves obtained on MOS capacitors (3x3µm2) with a (a) 3.6 and (b) 5.3nm-thick HfO2 layer, annealed at 350ºC (squares) and at 800ºC (triangles). The I-V curve in
circles corresponds to a typical post-breakdown (BD) I-V characteristic as reference, which shows larger currents due to the loss of the dielectric properties of the gate stack. The gate current dispersion has been evaluated from the gate voltage at which a current of 20nA flows through the MOS capacitor, VI, which is included in table 3.1 (second
row).
(a) (b)
Figure 3.7. Examples of I-EOX curves obtained on MOS capacitors (Area of 9µm²) with
a (a) 3.6 and (b) 5.3nm thick HfO2 layer. Note that after the high temperature annealing
(800ºC, triangles), pre-BD conduction is higher and more erratic that that measured in samples with a low temperature annealing (350ºC, squares).
Note that two clear different behaviors can be identified in Fig. 3.7a and b, which correspond to amorphous and polycrystalline samples. In the amorphous structures (squares), before BD, the current follows the typical Fowler-Nordheim behavior for these kind of structures, with a very small dispersion, which slightly increases in thicker oxides (Table 3.1, second row), in agreement with the CAFM I-V curves (Fig. 3.5). However, in polycrystalline samples (triangles), at low fields, the gate conduction is larger than in amorphous gate dielectrics, with a very erratic and non-stable behavior (leading to larger VI dispersions, Table 3.1), suggesting different conduction modes,
which can change from sample to sample. At high fields, current increases even more, and show the typical post-BD behavior. Since in polycrystalline structures a larger nanoscale morphological and electrical inhomogeneity was observed due to the presence of GBs, the erratic behavior observed in these gate stacks at device level could be related to the differences in the electrical behavior of nanocrystals and GBs, the last ones being much more conductive (probably due to the high density of oxygen
0,0 2,5 5,0 7,5 10,0 10-12 10-10 10-8 10-6 10-4 0,0 2,5 5,0 7,5 10,0 10-12 10-10 10-8 10-6 10-4 typical post-BD pre-BD (800°C) pre-BD (350°C) I G [A] EOX [MV/cm] 3.6nm 0 2 4 6 8 10 12 10-12 10-10 10-8 10-6 10-4 10-2 0 2 4 6 8 10 12 10-12 10-10 10-8 10-6 10-4 10-2 typical post-BD pre-BD (800°C) pre-BD (350°C) I G [A] EOX [MV/cm] 5.3nm
MOS devices
vacancies [Bersuker 10b] located at these positions) and whose conduction mechanisms are still not clear. Note, moreover, that the total current through fully processed polycrystalline structures is larger than in amorphous samples (Fig. 3.7), which suggests that polycrystalline layers show a larger conductivity. This seems to be in contradiction with the CAFM currents (Fig. 3.5). Moreover, at the nanoscale, although the dispersion increases in the polycrystalline samples, the I-V curves measured with the CAFM didn’t show the erratic and non-stable behavior observed at device level (Fig. 3.7). This apparent contradiction, however, can be explained by taking into account the different areas analyzed in each case. At device level, the current through the complete gate area is measured (9µm2), which corresponds to the superposition of currents flowing through
about 104 spots like those measured with the CAFM (Fig. 3.4). That is, currents through all the leaky sites (probably at GBs) are measured which, in addition, could have suffered from a BD event during the measurement [Vanessa 11b]. Contrarily, at the nanoscale, a much reduced number of spots can be measured, so that the probability of finding such leaky or broken down sites is very small. Moreover, the reduced current dynamic range of the CAFM does not allow determining whether the spots broke down during their characterization. All these factors make not possible to draw definitive conclusions on the current absolute value, but only on its variability.
b) Impact of nanoscale variability sources on the reliability of MOS
capacitors
The impact of the polycrystalline microstructure of the high-k layer on the reliability of the MOS capacitors was also investigated by measuring the electrical field at which the structures break down, EBD, during a RVS (ramped voltage stress). The Weibull
distributions obtained on gate stacks with different HfO2 thicknesses and subjected to
annealing processes at different temperatures are shown in Fig. 3.8, which includes the corresponding values of the Weibull slope (β) and the electric field for 63% broken down capacitors (EBD,63%). Note that smaller electric fields and slopes (which
correspond to larger dispersions of EBD)are measured on the polycrystalline structures
(and on thicker oxides), that is, in those samples in which the variability observed at the nanoscale was larger. The reduction of β in the polycrystalline samples is of special relevance.
Since, from the percolation model, β is proportional to the number of traps needed to trigger BD [Suñé 11], the smaller value of β obtained in the polycrystalline samples indicates that, in this case, less traps have to be generated during the stress to create a BD path. This could be related to the fact that the as-grown polycrystalline structures already have a higher density of native defects (before the stress) [Raghavan 09], probably related to O-vacancies [Bersuker 10b], which favor the excess of leakage current measured in current maps [Vanessa 10]. Since less traps have to be generated during the stress, BD is triggered at smaller voltages (EBD,63%) in those devices with
polycrystalline high-k dielectrics. Therefore, these results indicate that the nanoscale variability sources (polycrystalline microstructure in particular) not only affect the variability of the electrical properties of non-stressed MOS devices, but also their reliability (PUBLICATION 1).
Figure 3.8. EBD Weibull distributions obtained after applying a RVS on MOS
capacitors with different HfO2 layer thickness and subjected to an annealing at different
temperatures. The Weibull parameters are also included in the figure.