In addition to the enhanced performance demonstrated in the previous section, we expect the degradation associated with the buildup of hot phonons in the channel, particularly at the drain side of the gate, to be reduced when the bias employed is that associated with minimum hot phonon lifetime. Furthermore, the InAlN system provides a unique opportunity for researchers to study the reliability of HFET structures in a material system that is not under tensile strain, which is fundamentally different than the existing
AlGaN-based HFETs. In this sense, we can expect the reliability of the InAlN-based structures to be even better than their AlGaN cousins since strain relaxation would not be a mode of degradation as the layers are not under strain. This paves the way for the buildup of hot phonons to be a major degradation mechanism in InAlN/GaN HFETs, and it is this mechanism and the mitigation of it through the tuning of the hot phonon lifetime which we will now demonstrate.
As we know, the nonequilibrium (hot) optical phonons have very low group velocity and as such tend to remain localized to the region where they are initially emitted, Figure 31. This means that at high fields, such as those present in an FET device, we expect phonons to actually build up in the region where they are being emitted (i.e. at the drain side of the gate where the field is largest). One can imagine that such a localized high density of phonons is likely a place where actual crystal defects may be formed. Subsequently, the formation of defects would cause observable changes in the performance of the transistor. Our aim is to observe the degradation of the performance of InAlN-based FETs as the devices are subjected to continuous operation under high fields for long periods of time. In our experiment, we controlled the electron density with the gate voltage and used gated Hall effect measurements for an estimation of the 2DEG density. Armed with this knowledge, we subjected the HFET devices to high field stress (VD=20V) in the dark at
room temperature. We stressed the devices for periods of time up to 20 hours, and observed the maximum drain current, peak transconductance, and channel access resistances every hour or half hour in order to quantify the device degradation.
Simultaneously, we measured the gate leakage current during the stress and observed the level of degradation, at a fixed electron density, as a function of the total charge passed
through the drain and the gate electrodes. In this vein, we can fairly compare degradation of the devices subjected to low, moderate, and high current.
For all devices subjected to high field stress we observed a general trend of a reduction of maximum drain current and peak transconductance, as well as an increase in channel access resistances as stress proceeded. These observations are consistent with other reports in which devices were subjected to high fields and subsequent hot electron
effects.147,148 149 150, , As plotting one of the parameters versus time would unfairly favor the low drain bias over the high drain bias (the assumption is that more current translates into more degradation since degradation should scale with the temperature in the channel— see Figure 24 and associated text—which is generally linear with the applied power151), we plotted the maximum drain current versus the cumulative current that has flowed rather than the time, Figure 42. We focus on the change in the maximum drain current as it is the most prominent feature of the degradation. The stress condition was VD=20V,
and VG ranging from -3.5V to -6.5V. The highest degradation (which is associated with
the largest changes in maximum drain current) takes place at high and low values of drain current, rather than being high for high drain current and low for low drain current, as would be expected if only the device temperature were driving the degradation.
0 2000 4000 700 800 900 1000 -3.5 -4 -4.5 -5 -5.5 -6 -6.5 Maximum Drain Current (mA/mm)
Total Current Density (mA-hr/mm)
V
GFigure 42. Maximum drain current measured as devices are subjected to DC biasing at VD=20V,
VG=varied for a nearly lattice matched InAlN layer (“B”). The lowest rates of degradation occur not
at highest or lowest currents, but at a moderate current, associated with the optimal 2DEG density. The maximum drain current is shown not as a function of time, but as a function of total drain current that has passed through the device.
In Figure 43, we replot the change in the maximum drain current for the specific case in which charge of 1500mA-hr/mm has passed through the drain. Here we have transformed the applied gate voltage to the measured value of the 2DEG density at each voltage, obtained from a gated Hall bar measurement. The stars in Figure 43 show the same albeit for devices wherein the drain voltage was reduced so that the drain–gate bias (VDG=24V)
is maintained in order to exclude possible degradation due to high VDG for devices
subjected to high negative gate bias, corresponding to electron densities below 9 x 1012 cm-3. Clearly, the degradation rate exhibits a minimum at electron densities around 1013
cm-2. This dependence on the 2DEG density shown in Figure 43 is strikingly similar to the dependence of the LO phonon lifetime on the 2DEG density, Figure 35. The figure
function of the average channel sheet density. This is despite the fact that at lower sheet densities, the devices are being subjected to lower power densities (and therefore channel temperatures)152 and additionally devices subjected to comparable lateral fields still tend to degrade at higher rates. As such, we propose that the buildup of hot phonons plays a considerable role in the device degradation.
7 8 9 10 11 12 13 14 15 5 10 15 20 25 30 35 Change in IDm ax (%)
Low Field 2DEG Density
Figure 43. (a.) Change in maximum drain current after subjecting devices to high field electrical stress. The change is given for devices which have passed 1500mA-hr/mm of charge. The electron density is controlled by the gate bias. The stars represent devices that were stressed at a reduced
drain voltage so that the devices were subjected to VDG=24V, which is the same as that employed for
the devices stressed with 2DEG density~10.5 x 1012 cm-2.
If the degradation were attributable to the buildup of hot phonons, the least degradation would be expected at the 2DEG density around 6.5 x 1012 cm-2 where the shortest lifetime
τph is expected, Figure 35. Our stress measurements show the weakest degradation for
slightly higher electron densities. This can be understood in light of the power dependence on hot phonon lifetimes presented in 2.5.e.i. Ungated Structures. Hot electrons tend to occupy a larger volume in real space when they gain energy from the electric field. Therefore, the “bulk” density of electrons decreases as the field applied to the channel increases. As a result, a higher 2DEG density is needed to reach the phonon–
plasmon resonance, and the minimum LO phonon lifetime is achieved at a 2DEG density exceeding the optimum value measured at low fields.
As a final endeavor in attributing the buildup of hot phonons as the primary degradation mechanism rather than some gate leakage related mechanism, we quantified the
degradation for all the devices in this study as a function of the total amount of charge which has leaked through the gate, Figure 44. No systematic degradation with the gate leakage is found; some devices suffer high degradation with little gate leakage, some suffer little degradation with high gate leakage. The lack of the dependence on the gate leakage leads us inevitably to conclude that the gate leakage is not a major contributor to the degradation for these devices.
0 20 40 60
0 20 40
Total Charge Through Gate (A-hr/mm)
Cha nge in I D (% )
Figure 44. The total change in drain current for all devices in this study versus the total charge passed through the gate. The lack of any discernable dependence of degradation on the gate leakage indicates that the primary degradation mechanism is not related to the gate leakage.
In summary, we have demonstrated the importance of the buildup of hot phonons on the reliability of HFET devices. Furthermore, we have demonstrated that the tuning of the hot phonon lifetime, simply through the application of suitable gate voltages in order to
addition to enhancing the device lifetime of HFET devices. It is critical to be cognizant of such effects in order to achieve the ultimate performance from GaN-based HFETs.