Chapter 1 introduces the background and motivation of this research, and highlights the research hypothesis and its novel contributions. This chapter also presents the structure of this thesis.
Chapter 2 first introduces reconfigurable devices, and clarifies their basic concepts. Then this chapter focuses on FPGAs (Field Programmable Gate Arrays), which are an important reconfigurable digital device. This includes FPGA programmable logic and routing architectures. This chapter emphasises that nowadays FPGAs are cluster-based, and routing architectures are usually island-styled. In order to provide a background for circuit clustering method research, it is defined as a cluster-based island style FPGA model.
Chapter 3 explains why Computer Aided Design (CAD) is important in FPGA design flow. A research based CAD flow is introduced. The definition, requirements and significances of circuit clustering are explained. The rest of this chapter reviews a number of state-of-the-art circuit clustering methods, and comments on their advantages and disadvantages.
is based on Darwin’s theory of natural selection. EC actually refers to a set of Evolutionary Algorithms (EAs), and the components of EA are introduced. The rest of this chapter focuses on Genetic Algorithms (GAs), and MultiObjective Genetic Algorithms (MOGAs). The MOGA is the major method that has been used to solve the FPGA circuit clustering problem in this research.
Chapter 5 introduces the Random VPack, RVPack, FPGA circuit clus- tering method. This chapter first reviews VPack algorithm in detail, and highlights how the randomnesses are injected in VPack to produce the RV- Pack. The experimental setups and result comparisons are presented in the rest of this chapter.
Chapter 6 presents Grouping Genetic Algorithm based GGAPack and GGAPack2 FPGA circuit clustering methods. These methods are top-down clustering methods. This chapter clarifies GA representations, genetic op- erations, fitness function designs and multiobjective selection schemes. For GGAPack2, it explains how the RVPack solutions are used in GGAPack2. The detailed experimental setups, results and result analysis are summarised. Chapter 7 proposes a new MOGA-based FPGA circuit clustering method, the DBPack. This method fixes problems that are identified in Chapter 5 – RVPack. DBPack clusters a circuit using a new bottom-up perspective. Simi- lar to GGAPack, it introduces GA representation, genetic operations, fitness function designs and the multiobjective selection scheme. The experimental setups, results and comparisons follow in this chapter.
Chapter 8 combines GGAPack and DBPack methods, and proposes HY- Pack, and T-HYPack – the hybrid FPGA circuit clustering methods. HYPack and T-HYPack are based on DBPack produced solutions, and use GGAPack method as a second optimiser. In T-HYPack, it also optimises the timing performance of a clustered circuit by incorporating a FPGA placement and routing. This work is carried out by an on-line optimisation approach, where a clustered circuit can be continuously optimised for the timing performance
on a targeted FPGA. The experimental setups, results and result analysis are included.
Chapter 9 summarises the findings of the proposed methods, and concludes this research. This chapter also highlights the future work.
Chapter 2
Reconfigurable Devices
2.1
Introduction to reconfigurable devices
With the continued rapidly increasing needs of complex electronic system design, the weaknesses of pre-defined Integrated Chips (ICs), or Application- Specific ICs (ASICs) are exposed, where these weaknesses include, for example, longer design-to-market time, higher testing cost and fixed function. It has to emphasise that the design, fabrication and testing of a new ASIC are the most expensive and crucial parts in the microelectronics industry. To meet many testing and research requirements, which required a large number of full- customisable devices, reconfigurable devices were appeared. Reconfigurable devices are normal ICs but these ICs supply with a number of configurable resources, which allow these devices to be configured, referred to as function updatable, as any type of circuit or for many applications, and therefore avoid reinvestments in design, fabrication and testing in the microelectronics.
The configurability of a digital system first appeared from the Pro- grammable Read-Only Memory (PROM), and developed through many other
logic devices such as the Programmable Logic Array (PLATM), Programmable
and Rose, 1996). Similar to basic electronic circuits, reconfigurable devices, also known as reconfigurable hardware, can be divided into analogue and dig- ital types. A typical reconfigurable digital device is the Field Programmable Gate Arrays (FPGAs), its counterpart in the analogue domain being the Field Programmable Analogue Arrays (FPAAs), and Field Programmable Transistor Arrays (FPTAs). The typical FPAAs are the Zetex (Zetex Corp., 1999), Lattice ispPAC series (Lattice Corp., 2000, 2001a,b,c) and Anadigm AN221E04 (Anadigm Inc., 2003) FPAAs. These devices allow the analogue building blocks of a circuit to be configured, for example current sources and operational amplifiers (OPAMPs). Some reconfigurable analogue devices also provide lower level configurations – transistor levels, the FPTAs, for instance JPL FPTAs (Stoica et al., 2000) and Heidelberg FPTAs (Langeheine et al., 2001), are the typical devices. This thesis focuses on reconfigurable digital devices, in particular FPGAs.
Due to specific needs, the arrangements of interconnects and reconfigurable fabric structure, where the fabric is defined as a set of reconfigurable building blocks, and the arrangement refers to an architecture, in reconfigurable de- vices can be different. However, their architectures can still be classified as linear, array, mesh, crossbar, data-path, etc. The details of these architec- tures are well introduced in Trefzer and Tyrrell’s book (Trefzer and Tyrrell, 2015), a book for reconfigurable hardware. On the configurable device, the configurable fabric structure is normally one of two types – homogeneous or heterogeneous structures. In a homogeneous structure, the configurable fabric is formed from identical configurable blocks, and these blocks are arranged in a regular fashion. In contrast, the heterogeneous structure means that, apart from some identical configurable blocks, the configurable fabric also contains a number of specialised blocks, known as hard macros. In addition to the reconfigurable fabric structures, another important parameter for the reconfigurable device is the granularity, which indicates the configurable level of the reconfigurable device. The granularity is usually defined at three levels. These are: fine-grained, medium-grained and coarse-grained. Table 2.1 shows that the configurable levels in digital and analogue configurable devices with
Table 2.1: The configurable levels in digital and analogue configurable devices with different granularities (Trefzer and Tyrrell, 2015)
Granularity Digital Recfg. Device Analogue Recfg. Device
Fine
Logic Gates, Transistors,
Loop-Up Tables, Current Mirrors,
MUXs... Differential Pairs...
Medium Flip-Flops, Memories, OPAMPs,
Multipliers... Comparators...
Coarse ALUs, Filters,
Processors... ADCs, DACs...
Recfg. = Reconfigurable MUXs = multiplexers
ALU = Arithmetic Logic Unit
ADC, DAC = Analog to Digital Converter, Digital to Analog Converter
different granularities.