For the purposes of discussion, it is assumed that the development task for a new module or board design is composed of four sequential stages:
84 PLANNING FOR DESIGN-FOR-TEST
(1) Product definition.
(2) Architectural design.
(3) Detailed design.
(4) Transfer to manufacture.
The following sections indicate, from a test viewpoint, the tasks that should be performed in each stage.
4.2.1. Product definition
In this stage, the specification for the module or board is produced. This will detail the functions to be performed, the operating speed or throughput, and some aspects of its physical appearance — for example, the fact that a double-height EuroCard is to be used or the types of connector to be provided.
To allow initial planning for design-for-test, the following information should be included in the product specification:
O A definition of the function or functions to be performed, including the characteristics of and relationship between signals at its external interfaces.
O An estimate of the total number of units to be manufactured over the product life, with the quantity to be manufactured on a year-by-year basis if possible.
•I Definitions of any features that must be included in the product to assist in the maintenance and diagnosis of the system of which it is a part. For example, to support field fault diagnosis to a replacable unit, it might be a requirement that a communications interface card (for example, Ethernet) be provided with various loop-back facilities.
O Definitions of any features to be included to allow the health of the module or board to be verified in the field (for example, power-up self-test).
O A statement of the assembly method to be used — surface-mount, dual-in-line/plated-through-hole.
• The expected performance of the production test program — the target fault types, the fault coverage, the run time (fault-free and including diagnosis), and the ATE types available.
O The 'budget' for design-for-testability. The aim here is to allocate a fraction of the total resources to design-for-test. For example, an amount of board area or a share of the total component cost should be allocated to design-for-test at the outset and relinquished for other use only if not required for that purpose. Too often, the designer uses all the available board space for circuitry required to meet the functional specification, with the result that none is left for
design-PLANNING FOR A TESTABLE DESIGN 85
for-test. Under these circumstances, little can be done to render the design testable. (The question of how much budget to allocate for design-for-testability is discussed further in Section 4.6.)
In addition, the target manufacturer and repair organization (if different) should be identified wherever possible. For high-volume products (say, 10,000+ units per annum) this is essential, because the greatest economy in design-for-test can be achieved only by tailoring the circuit design to the target ATE systems (see Section 4.5.3).
A checklist is included in the Appendix to help in recording the above information.
4.2.2. Architectural design
Alternative block-level designs for the circuit are explored and key design decisions are made. For example, a decision may be made on the microprocessor family to be used and/or whether custom ICs will be used.
Increasingly, simulations are performed at a behavioural level as a part of this activity — for example, using VHDL (IEEE, 1987).
As a part of the design-for-test process, the following should be created and reviewed during this phase:
D An outline bill of materials (BOM) showing the key types of component that might be used (for example, the microprocessor family selected). This should be reviewed against any known testability requirements or known test problems, for example as advised by the target manufacturer based on prior experience. The Component Selection checklist in the Appendix can be used to assist in this review.
D Specifications for custom ICs, including a description of design features to be included to help test the loaded board — for example, ANSI/IEEE Std 1149.1 (IEEE, 1990).
G A test plan for the overall functional test or self-test of the complete product. This should detail the test to be performed, the way that the tests are to be applied, and the way that results will be observed.
While it should not specify precise test stimuli or responses, it should show the routes to be followed to get this data through the circuit to or from each component or functional block. Consider, for example, the RAM block of a microprocessor-based board design. The part of the test plan that deals with this block might specify that the ATE will drive and sense data via the microprocessor bus and that the microprocessor and other components should be disabled during this stage of the test so that this can be achieved.
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4.2.3. Detailed design
Detailed circuit schematics and board layouts are created, logic-level simulations are performed, and prototypes are constructed and debugged.
The testability of the design will be considered in detail during this stage and the following items should be created and reviewed:
O A final BOM showing the components used to construct the loaded board. As for the outline BOM, this should be reviewed against any known testability requirements or test problems.
O A complete documentation pack for the design, including a description of any design-for-test features added to help in testing.
Why spend time and money on design-for-test if you're not going to tell the test engineer what you've done?
O Test waveforms for any custom ICs or programmable devices (for example, PLAs) included in the design.
• A functional test for the complete board design. This,is the detailed implementation of the test plan created during the previous stage.
The precise patterns of Is and Os that will be applied and sensed have now been computed.
4.2.4. Transfer to manufacture
The finished design is transferred to the selected manufacturer. The following test-related activities will occur during this stage:
O Identification of the target manufacturer and (where appropriate) repair organization, if not identified previously. Note that this decision can only be left until this late stage in cases where the design does not 'push' any limits. For example, it should not include any timing-critical signal paths, use novel components, or have smaller than average board geometries. It should, in fact, be a perfectly average design.
• Conversion of tests for custom ICs and programmable components and of the functional test for the complete board into the formats required by the target ATE.
O Extraction of data from the printed circuit layout to permit construction of a test fixture.