PRECIOS MEDIOS ANUALES DE VENTA AL PÚBLICO DE GASÓLEOS

Two additional stages are required to perform analysis on the final design; parasitic extraction and static timing analysis. The former is performed using Synopsys StarRCXT. This is the same tool used in the cell characterization workflow and is performed on the exported design. This gives greater accuracy to the static timing analysis.

The static timing analysis is performed using Synopsys PrimeTime. Figure 68 shows the workflow. The first two stages of defining the core configuration and defining the target technology node are the same as previous workflows. The next stage imports the post layout Verilog netlist from the synthesis stage. The netlist is then annotated with the RC parasitics extracted during the parasitic extraction workflow. Three corners are generated during the extraction workflow; RC Best, RC Worst and Typical. All three corners are run during static timing analysis. The RC worst corner was used for sign off to ensure functionality [95].

The timing parameters are then defined including the derate values and analysis options. The static timing analysis is then performed. Once completed, the generated timing data is written out in the IEEE defined Standard Delay Format (SDF) to be used during post- layout simulation workflows. Finally, human readable reports are generated. These include reports for skew, latency and transitions times, as well as overall coverage and any bottlenecks. Most importantly, reports are generated detailing the fastest 10 paths in the design and the slowest 10 paths in the design. The latter report is used to determine whether all paths met the timing criterion and if not, determine the Worst Case Negative Slack (WNS) of the design.

Thus far, no inherent methodology of determining the maximum frequency (minimum clock period) for a given PVT corner has been described. The reason for this is that the tools are simply not designed to perform in this manner. W hen commercially designing a digital circuit, the designer is invariably provided with a target frequency and modifies the design to meet this constraint.

An iterative methodology was therefore designed to perform this task. Figure 69 shows the methodology. Initially, an extremely relaxed clock period for the design is provided. The design is then synthesized using the MCMM Design Vision synthesis workflow outlined in Section 5.7.1. The cells are then placed using the IC Compiler automated placement workflow outlined in Section 5.7.2. Clock tree synthesis is then performed using the CTS workflow outlined in Section 5.7.3. The Routing workflow in Section 5.7.4 finalizes the design stages. The design is then exported using the workflow outlined in Section 5.7.5. Parasitic extraction is performed using the workflow from Section 5.9 and finally static timing analysis performed using the workflow from Section 5.9. The WNS for the critical path is determined for the entire run from the timing analysis reports. If all paths meet the provided clock period or the WNS is less than 5% of the provided clock period, the clock period is reduced and the whole methodology iterated. If the WNS is 5% of clock period, this period is determined as the maximum frequency of operat ion. The 5% watershed was an arbitrary value chosen for the experiment. The primary reason for this value is that the synthesis tools are notorious for non-deterministic performance. As the tools are designed simply to meet a provided clock constraint, once this target is met, little optimization is performed afterwards other than leakage recovery. If the same design is provided with a more stringent timing target, the tools work harder to meet that target. Therefore, there is no linear relationship between provided clock period constraints and WNS. Moreover, this is compounded by the tools freedom of design choice. It is completely feasible that for a chosen clock period, a synthesized circuit type fails to meet the target, only for a tighter constraint to be applied, a new circuit type option to become available and the clock target to be met. The 5% value allows enough room in the

synthesis runs to allow the synthesis tools the freedom of design, whilst obtaining a high value of certainty that no other synthesis choice will provide a faster design. Moreover, for a signed-off circuit, 5% is a marginal amount to increase the clock frequency by in order to attain stable functionality. Whilst figure 69 shows that the methodology stops at 5%, for the aforementioned reasons, several runs were performed beyond the 5%

The methodology was performed for all three libraries. Figure 70 shows the results. The ARM Low Energy library produced a maximum frequency of 23.5 KHz from a clock period of 42550 ns. At this point, the WNS was 4.5% of the clock period. Beyond this point, no run produced a value less than 5%. The individual points show the non- conformity in the WNS over frequency, most notably the 22.72 KHz point produces a WNS less than the previous run of 22.22 KHz. It is likely that at this frequency point, the tool is able to synthesize a circuit variation it is incapable of synthesizing at the lower frequency point.

The Full Diffusion RVT library produced a maximum frequency of 42.88 KHz from a clock period of 23320 ns. At this point, the WNS was 4.2%. The next run period of 23310 ns produced a WNS of 8%. The difference in WNS between two clock constraints of such proximity again suggests the synthesis tool is only able to produce certain circuit choices under certain clock constraints.

The Full Diffusion multi-Vt library produced a maximum frequency of 414.94 KHz from a clock period of 2410 ns. The WNS for this run was 5%. The 2400 ns run produced a WNS of 5.6%, again expressing the non-conformity in the synthesis process.

There are a few important points of consideration from the experiment. The first is that on a ‘like-for-like’ basis, the maximum frequency of the Full Diffusion RVT library was 1.83X faster than ARM’s Low Energy library. This means that even for circuits with complexity running at around 7000 gates, the potential benefit of the full diffu sion sizing strategy measured on a cell for cell basis is still observable.

The second is that the Full Diffusion multi-Vt run had a maximum frequency 9.63X faster than the equivalent than the Full Diffusion RVT only run and 17.66X faster than the ARM library. Unsurprisingly, the multi-Vt run is therefore clearly the choice for circuit speed. The underlying information from the run provides more details of interest. When pushed to the frequency limits, the synthesis tool chose to implement the design using 94.45% of the cells from the LVT library and the remaining 5.55% from the RVT library. This shows that the synthesis tool is displaying the correct behavior for frequency critical multi-vt synthesis.

Whilst this methodology proved successful at determining the maximum frequency, it was time consuming and only accurate to within 5%. Faster and more accurate