Presentación de estados financieros

Config. (4, 1) (J) (2, 2) (J) (1, 4) (J) Our (J) Energy 325.504 558.459 711.643 729.287

Impr. 124.05% 30.59% 2.48% -

Table 3.2 Energy stored in HEES for real solar irradiation

In this section, we integrated a real solar irradiation profile [39] as the power input to our system. We start charging the system from 11:00am to 12:00pm when the solar irradiance reaches its maximum value. As Table 2.2 shows, in this charging profile, our algorithm outperforms the baseline algorithm with previously mentioned three configurations by 124.05%, 30.59% and 2.48% respectively. During the charging process, the bank terminal voltages of configuration (4, 1) and (2, 2) exceeds the input voltage of the DC-DC converters for a long time, which means they spend a large portion of time in boost mode which has low energy efficiency. As a result, large amount of energy wasted on DC-DC converters and less amount of energy is stored in the HEES bank for future use. We again compare the discharging time after this charging process. The proposed algorithm last 140.22%, 34.02% and 5.29% longer compared to (4,1), (2,2) and (4,1) configuration respectively.

3.5 Chapter Summary

In this chapter, we proposed an efficient heuristic algorithm for the energy efficiency optimization problem of charge allocation and replacement in an EHS/HEES equipped embedded system. Our goal is to minimize the energy wa sted on the DC-DC converters while

maximizing the energy stored in the HEES system. To avoid the complexity of iteratively searching the optimal operating point, we developed an approximation power model of the DC- DC converter. Based on this model, our algorithm tries to match the input and output voltages of

the DC-DC converters by dynamically adjusting the V_!! of the embedded load, the charge

transfer interconnect voltage V_!"# and the storage bank terminal voltage using reconfiguration. Experimental results show that our algorithm could store up to 124.05% more energy during charging process and last up to 140.22% longer.

Task Scheduling and

Chapter 4

Mapping for Applications on

Heterogeneous Multi-Processor

Systems

When the harvesting power is short, the load demands are supported by the EES bank only. Many works have been proposed to reduce the power dissipation on the battery-powered devices and systems. In this chapter, we will discuss the task mapping, scheduling and Dynamic Voltage and Frequency Scaling (DVFS) algorithms on the heterogeneous system, which is one of the solutions to raise the system performance and improve the energy efficiency.

Many real time applications demonstrate uncertain workload that varies during runtime. One of the major influences of the workload fluctuation is the selection of conditional branches which activate or deactivate a set of instructions belonging to a task. Many techniques have been proposed that perform power aware task mapping, ordering and DVFS for applications with fixed workload [23][49][50]. However, they may not achieve their best performance with real life applications that demonstrate workload variations. This work considers task scheduling and voltage selection of applications with variable workload on a heterogeneous multiprocessor system-on-chip. We focus on the set of applications which can be decomposed into repeated

tasks with relatively constant execution time. The uncertainty of the workload is reflected by the random activation and deactivation of certain tasks during run- time and it is captured by branch selections among tasks. We assume that such branch information is observable to the scheduling software to assist runtime scheduling and power management of the system. Examples of such task level branching include branches that enable or disable IDCT function during MPEG decoding or branches that select different modulation schemes for preamble and payload based on 802.11b physical layer standard. We model an application with dynamic branch selections using a conditional task graph (CTG). In this work, we capture the workload dynamics using Conditional Task Graph (CTG) and propose a set of algorithms for the optimization of task mapping, task ordering and dynamic voltage/frequency scaling of CTGs running on a heterogeneous multicore system.

We study the power aware task mapping and scheduling techniques for the CTGs with a particular interest in their performance on the heterogeneous multi-core system. It is important to investigate the low power techniques for the heterogeneous multi-core system, not only because it is the architecture of many embedded computing systems such as the Pasta sensor node [51], the LEAP system [52], and the mPlatform [53], but also because, due to the within-die variation and transistor wear-out, a homogenous multi-core system will exhibit heterogeneity over time [54].

The proposed framework optimizes the task mapping, task ordering and dynamic voltage/frequency scaling of CTGs running on a heterogeneous multi-core system. Due to the probabilistic branching, the execution of CTG is a random process. Our goal is to minimize the mean power consumption instead of the worst case power consumption of the application while meeting the hard real-time constraint. Our mapping algorithm balances the latency and the

energy dissipation among heterogeneous cores in order to maximize the slack time without significant energy increase. Our scheduling algorithm minimizes the mean power consumption of the application while maintaining a hard deadline constraint. Our DVFS algorithm dynamically distributes slacks during runtime, and achieves comparable energy reduction as the solutions found by non-linear mathematical programming. Due to its capability of slack reclaiming, our DVFS technique is less sensitive to the slight change in hardware or task execution and works more robustly than the conventional DVFS techniques. Compared to the existing works, the uniqueness of our approach can be summarized as the following:

• The proposed framework optimizes task mapping and scheduling simultaneously. We modify the Dynamic Level based Scheduling (DLS) algorithm [55] to find mapping and scheduling of CTGs on a heterogeneous platform. The complexity of task mapping and ordering is O(MN) where M is the number of processing elements (PEs) in the system and N is the number of tasks in the task graph.

• We consider the application with conditional execution as a random procedure in which the branch selection probabilities can be profiled (or measured). Our algorithm utilizes such statistical information in each optimization step to reduce the mean power consumption.

• The proposed slack reclaiming based DVFS algorithm has pseudo-linear complexity with the respect to the number of tasks in the CTG. It also performs more robustly than the DVFS solution found by mathematical programming.

The rest of this section is organized as follows: section 1 presents related works; section 2 introduces the application and hardware architecture models; section 3 and section 4 present in detail the underlying scheduling, mapping and DVFS algorithms. Section 5 gives the

experimental results. Finally, section 6 concludes the work.