PROBLEMA DE INVESTIGACIÓN

This project has provided a framework for future possible ADH projects to extend the functionality of the language and also to tackle the current bugs. It also provides research areas to do with the other related issues.

The clocking and the timing analysis is one aspect that we have not considered in this thesis. The timing is one of the major issue in digital hardware and a programmer might want to get hold of the clock signal and do something with it. It should be included in the language syntax to explicitly capture the master clock so a programmer can use it appropriately.

The automated VHDL production might waste some of the hardware resources (number of logics used) compared to human written VHDL. A possible solution to this could be found through optimisation techniques or directly generating netlists without producing the VHDL codes.

9.2. Future work 109

as Integer and Real by the compiler, and their affect on the SNR (Signal-to-Noise Ratio) could also be investigated.

Finally, the dynamic aspect features based on intermediate-stage code-graph modification could provide more powerful weaving.

In summary, the future work areas are given as follow:

• Tackling the bugs in the current compiler to increase the stability and usability

• Implementation of the library functions

• Refactoring and re-designing some of the classes

• Performance evaluation

• Optimisation techniques

• Dynamic aspect feature implementation

• Variable Integer-width and SNR

• Bypassing the VHDL generation and directly generating the netlist

The listings are given in order of importance. As the compiler is still not in 100% working order, the remaining bugs should be tackled first followed by either the implementation of the library functions or the refactoring and re-designing some of the components. Some re-design proposals have been described throughout the compiler implementation chapters, Chapter 5, 6, and 7. When this is done, the compiler should be able to produce synthesizable hardware devices, which is where the performance evaluation could be carried out.

Appendix A

BNF of ADH

NON-TERMINALS

TranslationUnit ::= ( ClassDefinition | AspectDefinition | SetDefinition )* EndOfFile

EndOfFile ::= ( "." | <EOF> )

ClassDefinition ::= ( VisibilityDefinition <CLASS> Identifier <OPENBRACE> ( AttributeDeclaration |

ConstructorDeclaration | MethodDeclaration )* <CLOSEBRACE> )

AspectDefinition ::= ( VisibilityDefinition <ASPECT> Identifier <OPENBRACE> ( StaticIntroduction |

AttributeDeclaration | MethodDeclaration | PointcutDeclaration | AdviceDeclaration )* <CLOSEBRACE> )

SetDefinition ::= ( VisibilityDefinition <SET> Identifier <OPENBRACE> ( Identifier <SEMICOLON> )* <CLOSEBRACE> )

VisibilityDefinition ::= ( <VISIBILITY> )?

AttributeDeclaration ::= ( VisibilityDefinition EntityType Identifier EntityDimensions ( <ASSIGN> Initializer )? ( <COMMA> Identifier EntityDimensions ( <ASSIGN> Initializer )? )* <SEMICOLON> )

EntityType ::= ( <IDENTIFIER> )

EntityDimensions ::= ( <OPENBRACKET> Expression <CLOSEBRACKET> )* Initializer ::= ( Expression | <OPENBRACE> ( Expression ( <COMMA>

Expression )* )? <CLOSEBRACE> )

ConstructorDeclaration ::= ( VisibilityDefinition Identifier InputArguments StatementBlock )

MethodDeclaration ::= ( VisibilityDefinition <METHOD> OutputArguments <EQUAL> Identifier InputArguments

StatementBlock )

OutputArguments ::= <OPENPARENTHESIS> ( AttributeDeclaration )* <CLOSEPARENTHESIS>

InputArguments ::= <OPENPARENTHESIS> ( AttributeDeclaration )* <CLOSEPARENTHESIS>

PointcutDeclaration ::= ( VisibilityDefinition <POINTCUT> Identifier InputArguments <COLON> <CALL>

<OPENPARENTHESIS> <METHOD> OutputArguments <EQUAL> MethodReference InputArguments <CLOSEPARENTHESIS> <SEMICOLON> )

AdviceDeclaration ::= ( <BEFORE> | <AFTER> | <AROUND> ) InputArguments ( <COLON> Identifier InputArguments StatementBlock ) StaticIntroduction ::= ( StaticVariableIntroduction |

StaticMethodIntroduction )

StaticVariableIntroduction ::= ( VisibilityDefinition ( EntityType MethodReference EntityDimensions ( <ASSIGN> Initializer )? ( <COMMA> Identifier EntityDimensions ( <ASSIGN> Initializer )? )* ) <SEMICOLON> ) StaticMethodIntroduction ::= ( VisibilityDefinition <METHOD>

OutputArguments <EQUAL> MethodReference InputArguments StatementBlock )

Appendix A. BNF of ADH 113 StatementBlock ::= ( <OPENBRACE> ( AttributeDeclaration )* (

StatementBlock | Statement )* <CLOSEBRACE> ) Statement ::= ( ConditionalStatement | StateMachine | WhileStatement

| DoWhileStatement | ForStatement | OutputConnection <SEMICOLON> | InputConnection <SEMICOLON> |

MultiAssignment <SEMICOLON> | PreIncrement <SEMICOLON> | PreDecrement <SEMICOLON> | PostIncrement <SEMICOLON> | PostDecrement <SEMICOLON> | AssignmentStatement <SEMICOLON> | Call <SEMICOLON> | NewObject <SEMICOLON> | <SEMICOLON> )

ConditionalStatement ::= ( <WHEN> <OPENPARENTHESIS> Expression <CLOSEPARENTHESIS> StatementBlock ( <OTHERWISE> StatementBlock )? )

StateMachine ::= ( <STATE> <OPENPARENTHESIS> ReferenceName <COMMA> ReferenceName <CLOSEPARENTHESIS> <OPENBRACE> ( TransitionRule )+ <CLOSEBRACE> )

TransitionRule ::= ( Identifier <TRANSITION> Identifier <WHEN> <OPENPARENTHESIS> Expression <CLOSEPARENTHESIS> <SEMICOLON> )

WhileStatement ::= ( <WHILE> <OPENPARENTHESIS> Expression <CLOSEPARENTHESIS> StatementBlock )

DoWhileStatement ::= ( <DO> StatementBlock <WHILE> <OPENPARENTHESIS> Expression <CLOSEPARENTHESIS> <SEMICOLON> ) ForStatement ::= ( <FOR> <OPENPARENTHESIS> ReferenceName <ASSIGN>

Range <CLOSEPARENTHESIS> StatementBlock )

OutputConnection ::= ( <CONNECTION> <OPENPARENTHESIS> <STRING_LITERAL> ( "," <STRING_LITERAL> )* <CLOSEPARENTHESIS> <ASSIGN> Expression )

InputConnection ::= ( ReferenceName <ASSIGN> <CONNECTION> <OPENPARENTHESIS> <STRING_LITERAL> ( "," <STRING_LITERAL> )* <CLOSEPARENTHESIS> )

AssignmentStatement ::= ( ReferenceName <ASSIGN> Expression ) MultiAssignment ::= ( <OPENBRACKET> ParameterReturnList

<CLOSEBRACKET> <ASSIGN> Call )

ParameterReturnList ::= ( ReferenceName ( "," ReferenceName )* ) Call ::= ( ReferenceName <OPENPARENTHESIS> ParameterAssignmentList

<CLOSEPARENTHESIS> )

ParameterAssignmentList ::= ( Expression ( "," Expression )* ) NewObject ::= ( <NEW> ReferenceName <OPENPARENTHESIS>

ParameterAssignmentList <CLOSEPARENTHESIS> ) PreIncrement ::= <INCREMENT> ReferenceName

PreDecrement ::= <DECREMENT> ReferenceName PostIncrement ::= ReferenceName <INCREMENT> PostDecrement ::= ReferenceName <DECREMENT>

Range ::= Expression <ELLIPSE> Expression ( <COMMA> StatementBlock )? Expression ::= ( InclusiveOr ( <WHEN> <OPENPARENTHESIS> InclusiveOr

<CLOSEPARENTHESIS> ( InclusiveOr <WHEN>

<OPENPARENTHESIS> InclusiveOr <CLOSEPARENTHESIS> )* ( InclusiveOr <OTHERWISE> )? )? )

InclusiveOr ::= ExclusiveOr ( <OR> InclusiveOr )? ExclusiveOr ::= And ( <XOR> ExclusiveOr )?

And ::= Equality ( <AND> And )?

Equality ::= Relational ( <EQUALITY> Equality )? Relational ::= Shift ( <RELATION> Relational )? Shift ::= Add ( <SHIFT> Shift )?

Add ::= Multiply ( <ADD> Add )?

Multiply ::= Unary ( <MULTIPLY> Multiply )? Unary ::= ( ( <NOT> | <ADD> )? Primary )

Primary ::= ( <OPENPARENTHESIS> Expression <CLOSEPARENTHESIS> | Constant | NewObject | PreIncrement | PreDecrement | ReferenceName | PostIncrement | PostDecrement | Call ) ( <OPENANGLE> Range <CLOSEANGLE> )?

Appendix A. BNF of ADH 115 ReferenceName ::= Identifier ( <OPENBRACKET> ( Range | Expression )

<CLOSEBRACKET> )* ( <DOT> Identifier ( <OPENBRACKET> ( Range | Expression ) <CLOSEBRACKET> )* )*

Identifier ::= ( <IDENTIFIER> )

Constant ::= ( <INTEGER_LITERAL> | <STRING_LITERAL> | <BOOLEAN_LITERAL> )

Appendix B

VHDL Tutorial

This section describes basic syntax of VHDL language and is basically a tutorial covering how to programme in VHDL. However, this is a very important section because the back-end of this project produces VHDL language; hence, deep under- standing of VHDL language is required. In Chapter 7, the back-end generation, a few references to this tutorial were made rather than describing the syntax of VHDL again.