El proceso político de las conferencias y las narrativas institucionales

The addition of a passivation layer on the IGZO TFTs required modifications to the process flow. The alumina was etched in 10:1 BOE down to the Al source/drain and gate

Figure 15: ICD layout, with twelve interdigitated fingers extending across the IGZO mesa. Each gated region has a width of 44 µm, and 5 µm side overlaps between the top-contact metal and the bottom-gate metal. The total gated area is ~ 0.002 cm².

Bot tom -Ga te Top -Co n tact

contacts, which caused the Al surface to roughen (blackened) as shown in Figure 16. There was a concern that the Mo underneath the roughened Al will become oxidized during the passivation anneal and the yield was low; thus a new process integration strategy was needed.

Figure 16: Al contacts after alumina etch in 10:1 BOE

Several approaches were made to solve the problem. One approach was to increase the thickness of the Mo layer and drop the Al that would be on top. The Mo was then tested to see if it would oxidized under the alumina layer. It was found that Mo does oxidize at temperatures T > 350 °C with only 50 nm of Al2O3 on top of it. It was also found that the etch rate of Mo in pad etch and 10:1 BOE is negligible, thus it would make for a suitable etch stop for etching alumina. The original sputter recipe (200 W) for Mo was adapted from an old stationary sputter onto LOR so as to not burn the resist. The previous process involved rotating the wafers resulting in a much lower deposition rate, and doubling the time to the current sputter process to double the thickness increased the stress such that the LOR underneath it started to delaminate causing the Mo to flake off. Different sputter recipes were investigated due to the uncertainty as to how much power could be utilized

25 µm

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before the resist would burn. The investigated sputter recipes are shown in Table 6. It was found that 1000 W does not burn the resist and the Mo lifted-off with no issues. The higher power (1000W) Mo sputter recipe was from the gate Mo sputter, and it was found to have the least amount of stress. This process resulted in poor devices.

Table 6: Mo sputter conditions and stress measurements

Material Power (W)

Pressure

(mTorr) Time (sec) Thickness (nm)

Another approach to solve the oxidation problem was to create a tri-stack of Mo/Al/Mo for the source, drain, and gate contact regions. The sputter recipe is shown in Table 6 and utilizing the 1000 W recipe. The Al sputter was also at high power, but the amount of time the resist could withstand that high power was uncertain. Thus, the sputter was broken into two 300 sec portions, and between all of the sputters there was a ten minute cooling period to ensure the resist would not overheat.

Unfortunately, the tri-stack did not work as a solution to the etch problem, by comparing a device fabricated with and without the tri-stack as depicted in Figure 17 to Figure 9, respectively, shows evidence of there being a problem, which was due to the mask and not the actual layers. It was overlooked that using the same mask level to create the contact cut to the gate and deposit the tri-stack, and then again utilize it to make the passivation open contact cut through the alumina was not going to work. It was originally thought that the gate dielectric (TEOS) would protect the gate Mo, even if there was some over etch. It was overlooked that during the gate contact cut and source/drain lift-off lithography the LOR was undercut by the developer twice making it such that a ring of gate

Mo was exposed around the tri-stack, and this can be seen in Figure 18. This undercut was enhanced by the seemingly slow etch rate of alumina. The work-around to the issue was to do the passivation open lithography and etch of the tri-stack after annealing; this mitigated the chance of any Mo oxidizing, and allowed leniency with the wet etch.

Figure 17: Overlay ID-VG transfer characteristic of an unpassivated IGZO TFT swept up and down with hysteresis. The dimensions are L = 24 µm and W = 100 µm.

Figure 18: Undercut of the gate contacts during Al2O3 etch.

1.E-13 1.E-12 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03

-5 0 5 10

Drain Curre nt (A)

Gate Voltage (V)

Channel Undercut

Gate Contact

10 µm

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Chapter 5

ELECTRICAL CHARACTERIZATION AND ANALYSIS

The electrical characterization of devices were conducted with a HP-4145B parameter analyzer to acquire the ID-VG transfer characteristic measurement on TFTs with a constant channel width (W) of 100 μm and various lengths (L) ranging from 6 to 48 μm. Unless otherwise noted the measurements were taken with a low to high gate voltage sweep, medium integration, and low-drain bias and a high-drain bias of 0.1 V and 10 V respectively. C-V characteristics from the IDCs were obtained using a Materials Development Corporation (MDC) system with an HP 4284A precision LCR meter.

Figure 19: Measured ID-VG transfer characteristics of TFTs without (left) and with (right) alumina passivation, with channel dimensions of L = 24 µm & W = 100 µm. The TFT without alumina passivation exhibited the following operating parameters: µch = 12 cm²/V•sec, VT = -0.3V, SS = 135 mV/dec. The TFT with alumina passivation exhibited the following operating parameters:

µch = 5 cm²/V•sec, VT = 0.3V, SS = 300 mV/dec.

Figure 19 depicts ID-VG curves of TFTs with and without alumina passivation. It was observed that the device without the passivation layer exhibits better device operation than the device with the alumina passivation layer. It was hypothesized that the device with passivation has some degree of defects causing the degraded performance. The origin of these defects were investigated through modeling and simulation.