Propósito de la demanda:

This section describes the relationship between use of the GIC virtual CPU interface registers and the GIC virtual interface control registers. See The virtual CPU interface on page 5-178 for more information about the virtual CPU interface.

To ensure system correctness when handling virtual interrupts, one of the following conditions must be true: • All Group 0 interrupts must have a higher priority than any Group 1 interrupt. That is, there is no overlap in

the priorities allocated to Group 0 and Group 1 interrupts. • The GICV_CTLR.AckCtl bit must be set to 0.

These conditions apply, also, to physical interrupts and the GICC_CTLR.AckCtl bit, see The effect of interrupt grouping on interrupt acknowledgement on page 3-50.

Note

ARM deprecates the use of GICC_CTLR.AckCtl and GICV_CTLR.AckCtl, and strongly recommends using a software model where GICC_CTLR.AckCtl and GICV_CTLR.AckCtl are set to 0.

In GICv2, ARM recommends that separate registers are used to manage Group 0 and Group 1 interrupts: • GICV_IAR, GICV_EOIR, and GICV_HPPIR for Group 0 interrupts

5 GIC Support for Virtualization 5.2 Managing the GIC virtual CPU interface

The operation of these registers is:

GICV_IAR and GICV_AIAR

The virtual machine reads GICV_IAR or GICV_AIAR to acknowledge an interrupt. A spurious interrupt ID is returned when:

• there is no interrupt to acknowledge

• a higher priority interrupt is ready to be acknowledged in the other group.

The normal GIC rule that interrupts must complete in the order that they are acknowledged on a CPU interface applies to both the physical and virtual CPU interfaces.

GICV_EOIR and GICV_AEOIR

The EOI request must write the Interrupt ID and CPUID values read when the interrupt was acknowledged. A write to the appropriate register, GICV_EOIR or GICV_AEOIR clears the preemption bit associated with the highest priority active interrupt in the Active Priorities Register,

GICH_APR:

• When the highest priority active interrupt is a Group 0 interrupt, writing the appropriate value read from GICV_IAR to GICV_EOIR:

— clears the preemption bit in GICH_APR

— if GICV_CTLR.EOImode is cleared to 0, removes the active state in the corresponding List register

— if GICV_CTLR.EOImode is cleared to 0 and the GICH_LRn.HW bit is set to 1, deactivates the corresponding physical interrupt in the Distributor

When the highest priority active interrupt is a Group 0 interrupt, the effect of writing to

GICV_AEOIR is UNPREDICTABLE.

• When the highest priority active interrupt is a Group 1 interrupt, writing the appropriate value read from GICV_AIAR to GICV_AEOIR:

— clears the preemption bit in GICH_APR, and

— if GICV_CTLR.EOImode is cleared to 0, removes the active state in the corresponding List register

— if GICV_CTLR.EOImode is cleared to 0 and the GICH_LRn.HW bit ==1, deactivates the corresponding physical interrupt in the Distributor

When the highest priority active interrupt is a Group 1 interrupt, the effect of writing to

GICV_EOIR is UNPREDICTABLE.

Table 4-37 on page 4-139 shows how GICV_AEOIR is affected by GICV_CTLR.AckCtl.

GICV_HPPIR and GICV_AHPPIR

For the virtual CPU interface:

• a read of GICV_HPPIR returns the Group 0 pending interrupt with the highest priority • a read of GICV_AHPPIR returns the Group 1 pending interrupt with the highest priority.

Table 4-42 on page 4-144 shows how GICV_HPPIR is affected by GICV_CTLR.AckCtl. The hypervisor uses the GICC_CTLR.EOImode bit to separate priority drop in the physical CPU interface and interrupt deactivation in the Distributor. The hypervisor can use GICC_DIR to deactivate interrupts, to retire them from the Distributor. The GICC_DIR is used to deactivate hardware interrupts in certain cases, and usually the

GICC_DIR operation is required for deactivating SGIs: • in the SGI N-N handling model

5 GIC Support for Virtualization

5.2 Managing the GIC virtual CPU interface

A virtual machine can deactivate interrupts in the following ways:

GICV_CTLR.EOImode == 0

The GIC deactivates hardware interrupts directly, that is, writing to GICV_EOIR drops the priority of an interrupt and deactivates it simultaneously. The GICH_LRn.HW bit indicates whether an interrupt is related to hardware or software, and therefore whether to forward the deactivate to the Distributor.

See List Registers, GICH_LRn on page 5-176 for more information.

GICV_CTLR.EOImode == 1

Writing to GICV_EOIR performs priority drop operation and writing to GICV_DIR performs the deactivate interrupt operation.

Note

• The limited context information available when a hypervisor handles a maintenance interrupt means that, if a hypervisor maintains more than one active interrupt in memory, instead of in the List registers, it must also trap virtual machine accesses to GICV_DIR, so that it can deactivate interrupts for the virtual machine.

ARM recommends that, as far as possible, the hypervisor manages active interrupts for the current virtual machine using the List registers.

• The GIC architecture requires that writes to GICV_EOIR are ordered so that a write to

GICV_EOIR always refers to the same interrupt as the most recent read of GICV_IAR. However, there is no requirement for writes to GICV_DIR to deactivate interrupts in any particular order.