Pruebas

The testbed uses a PPM format with 4 timeslots of equal duration (2 ns each) and an additional guard interval of longer duration (approx. 8.67 ns) resulting in a pulse repetition frequency (PRF) of (4·2 ns+8.67 ns)−1_{=60 MHz, cf.Figure 3.48.} Adopting the naming convention of [23], this modulation format can be called a combination of “x-frame PPM” and “x-pulse PPM.” The transmitted PPM signal s(t) can be modelled as s(t)= ∞ k=−∞ pt−Ak/10T−kTPRF−τ(t), (3.52)

where p(t) denotes the designed pulse shape,T = 2 ns is the timeslot duration,

and fPRF=1/TPRF=60 MHz is the PRF. The PPM symbols are denoted asAk∈

{0, 1, 2, 3}and each symbol is repeated ten times, see (3.52). The slowly varying delayτ(t) describes fluctuations in the PRF and clock jitter.

The transmitter design is shown in Figure 3.47a. It consists of a clock os- cillator which defines the PRF of 60 MHz and generates a stable timebase for the pulse positions within each symbol frame. A divider (denoted by “(: 10)” in

Figure 3.47) defines the number of repeated pulses sent per PPM symbol. A data generator produces a pseudorandom noise (PRN) bit stream (binary symmetric source) for measurement purposes. The data bits are mutually uncorrelated and equi-probable which ensures that the pulse positions are uniformly distributed within the 4 timeslots used for data transmission. The delay lines define the pulse positions within a symbol. A symbol switch selects the pulse position to be trans- mitted during each frame. Finally, a pulse shaping device creates the waveform. The pulse shaping is implemented by two high-frequency transistors (BFP 540F) which shape the rising edge of the delayed 60 MHz signal to the required narrow UWB pulse shape. A discone antenna designed for a center frequency of 5.8 GHz emits the pulses.

In the following, we discuss the transmitter components and measurements in detail.

Clock generator. The clock generator is a crystal oscillator that needs to be well decoupled from the noise emitted by other parts of the transmitter. The overall performance (bit error rate) of PPM is sensitive to the clock jitter variance. To illustrate this, we show the effect of a small ripple (in the range of millivolts) in the power supply of the crystal oscillator which can cause significant clock jitter.

Figure 3.49shows oscillograms of the observed signal at the receiver side with and without the supply voltage ripple.

Frequency divider. The divider is set to 10 and every PPM symbol is repeated ten times. This enables the receiver to average received symbols over ten realisations. This can be interpreted as a spreading gain of 10. In a future testbed enhancement, this simple repetition code can be replaced by a time-hopping spreading sequence to identify the user of interest in multiple-access scenarios.

Pseudorandom noise data generator. For the experiments, a two-bit wide pseudo- random noise (PRN) data generator is implemented. The data are generated for measuring the link performance by counting bit errors for bit error rate (BER) measurements. In a future implementation step, this data generator will be re- placed by an external source providing, for example, encoded multimedia data streams.

Delay lines. The demonstrator uses an integrated circuit 3D3215 (Data Delay De- vices Inc.). This component implements five equally spaced taps ofT=2 ns delay each. In the testbed, it is driven at almost its maximum usable frequency and some delay tolerances have been observed. Delay variations are also due to differences in the capacitive loads due to the circuit layout. These load differences have been eliminated by introducing small parallel capacitors.

Symbol switch. The symbol switch consists of a symbol latch and a 4 to 1 mul- tiplexer. The two data bits are latched first and then control the address of the

Data generator PRN : 10 2 CPLD XC2C32 60 MHz

clock Digital delay IC. 3D3215, ´a T=2ns

T T T Symbol switch RF 2x BFP540F Discone antenna (a) (b)

Figure3.47. (a) Block diagram of the transmitter; (b) Realisation.

multiplexer. The outputs of the 3D3215 delay taps are connected to the data inputs of the multiplexer. It proves to be important to switch among the inputs whenall input signals have high state. If this condition is violated, an additional rising edge is generated resulting in spurious pulses.

Figure 3.48 shows the measured 4-ary symbol pulses after the first pulse shaper transistor stage. In this figure, we also observe a small spurious pulse. This is caused by switching the multiplexer from an input with a low signal to one with a high signal. In the testbed, these spurious pulses occur only once every 10TPRF ≈166.7 ns when the transmitter modulates a new pair of data bits which is distinct from the previous bits.

The digital part of the PPM transmitter is integrated into a complex pro- grammable logic device (CPLD, CoolRunner II, XILINX Inc.) which generates very fast rising edges. The subsequent pulse shaper steepens the rising edges using a high-pass filter.

Pulse shaper. For the pulse shaper, two stages of high-frequency transistors (BFP 540F) with grounded emitters are used. Every stage has a highpass RC filter at its input and a shorted microstrip line at the output for shortening the amplified pulse. The shorted microstrip line in the first stage is much longer than in the

Ch2 500 mVΩ M 2.0 ns 25.0 GS/s

A Ch1 / 1.76 V

ET 40.0 ps/pt

Tek Stopped 1575170 Acqs 30 Nov 0415 : 23 : 01

TPRF≈16.667 ns T=2 ns (a) Start 0 Hz 1 GHz Stop 10 Hz Date : 09.Dec.2004 14 : 35 : 19 Market 1 [T1] RBW 3 MHz RF Att 10 dB −34.38 dBm VBW 3 MHz 6.97995992 GHz SWT 58 ms Unit dBm Ref Lv1 0 dBm 1 AP 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 (b)

Figure3.48.(a) Modulated symbol pulses after the first pulse shaper stage. (b) Spectral power density of the PPM signal.

second otherwise the amplitude of the pulse would decrease significantly. The col- lector resistance is chosen to produce a low output resistance and to allow a high PRF. The UWB transmitter generates pulse peak voltages of nearly 3 V at 50Ω with a pulse width well below 100 ps (measured at half amplitude).

Antenna. Traditional broadband antennas are designed with multiple resonant structures which cause excessive ringing and group delay distortion (e.g., log- periodic Yagi-Uda antenna). Several antenna types were designed and evaluated

Ch1 200 mV Bw M 10.0μs125 MS/s

A Ch1 / 432 mV

8.0 ns/pt

Stopped 39271 Acqs 19 Oct 04 08 : 42 : 06

(a)

Ch1 200 mV Bw M 10.0μs125 MS/s

A Ch1 / 376 mV

8.0 ns/pt

Stopped 207978 Acqs 19 Oct 04 09 : 06 : 26

t1 :−37.46μs

t2 : 13.62 ns

Δt: 37.47μs

1/Δt: 26.69 kHz

(b)

Figure3.49. Influence of transmitter clock jitter on the received signal: (a) with; (b) without jitter. This is an oscillogram with vertical histogram function.

by measurements to find a practical UWB antenna solution. Such an antenna so- lution should result in a narrow pulse response without ringing or introducing ad- ditional echoes. Such echoes occur due to imperfect matching between the trans- mitter output and the antenna input. Antenna mismatch causes part of the pulse power to be reflected repeatedly between antenna connector and the second trans- mitter’s collector. A 6 dB attenuator is included between the second transistor and the antenna connector for reducing such echoes.

UWB impulse radio transmitters need to be placed near (or even inside) the antenna to cope with mismatch problems and the resulting echoes.