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The first step in analyzing the system characteristics is to obtain the channel models used to describe the system interconnects, using a system identification (SID) technique [63]. The model identification will be performed using several known system identification methods from the fields of radio-frequency (RF) and digital signal processing (DSP) engineering. The advantages and disadvantages of the various methods will be compared and contrasted, and a single system identification method will be selected as the one to be utilized from this point forward.

Figure 4-1 shows the test circuit that will be used to compare the various system identification methods. The circuit consists of lumped circuit elements to represent packaging parasitics, and a lossy transmission line distributed circuit element to represent what would most commonly be stripline or microstrip transmission line structures in a printed circuit board, package substrate, or other form of electronic packaging for an integrated circuit chip [1].

Figure 4-1: Test Circuit with Lumped Elements and Transmission Line with Precise Distributed Element Representation

Note that the ladder network representation of the transmission line in Figure 4-1 is comprised of an infinite number of sections that are infinitesimally small, with Δ𝑧 → 0, which leads to a description of the transmission line with partial differential equations, in accordance with distributed circuit theory of transmission lines [6]. As such, it must be

1 nH 100 mΩ 1 pF 2 nH 200 mΩ 1.5 pF ∆z→ 0 G∆z R∆z L∆z L∆z C∆z R∆z G∆z C∆z l = 5.0 in. ∆z→ 0

lumped elements, as indicated by the fact they are expressed in per unit length quantities which must be multiplied by Δ𝑧 to have normal resistive, capacitive, and inductive units.

The depiction of the test circuit of Figure 4-1, while mathematically precise, is not a convenient circuit schematic representation for repetitive use. Figure 4-2 shows a more convenient and typical representation of the test circuit, with the ladder network representation of the transmission line element of Figure 4-1 replaced with the cylindrical symbol representing the transmission line [1], [7]. This symbol will be used for distributed transmission line elements throughout the remainder of this project.

Figure 4-2: Test Circuit with Lumped Elements and Transmission Line with Convenient Electrical Schematic Representation

It should be emphasized that the test circuit as defined in Figure 4-1 and Figure 4-2 is intentionally arbitrary, and is thus somewhat oversimplified as compared to a real channel model encompassing the entire signal path in a typical electronic system. Such a model often includes the overall path from a controlled-collapse chip connect (C4) on the sending module, through 1st- and 2nd-level packaging, and finally terminating at the C4 on the receiving module.9 The values of the lumped elements were chosen as a reasonable representation of parasitic effects of the electronic packaging, such as connectors, solder connections, and terminal leads. The presence of the transmission line is important for studying the effects of attenuation, dispersion, and propagation delay in the system, as these effects are frequency-dependent and thus non-intuitive in nature [16], [17], [74].

The simplified model shown includes four reactive lumped elements. Without the transmission line element, it is easily seen that the system’s transfer function in the

9

The term “controlled collapse chip connect” and associated C4 acronym are most commonly used within IBM Corporation. The more common term in the industry at large is “flip chip.”

1 nH 100 mΩ 2 nH 200 mΩ

1 pF Zo=50 Ω, Td=172 ps/inch 1.5 pF length=5.0 in. (12.7 cm)

complex frequency domain, 𝐻_𝑎(𝑠), would consist of a 4th-order rational polynomial [40]. The addition of the transmission line element introduces attenuation, dispersion, and delay into the system [6], and significantly complicates the form and order of 𝐻_𝑎(𝑠), leading to a rational function of higher order to account for the propagation delay [74]. Nevertheless, the test circuit of Figure 4-2 will be referred to as the “4th-order test circuit with delay” or, often, as simply the “4th-order test circuit.”

For the test circuit of Figure 4-2, a typical signal integrity analysis would consist of a time-domain simulation performed in SPICE or a similar tool [2], [72]. The simulation would be performed by assuming the test circuit of Figure 4-2 as the channel interconnect model, and by applying a driver circuit model at the input and a receiver circuit model at the output. Figure 4-3 shows the overall circuit including the driver, interconnect, and receiver load circuit models, with circuit nodes labeled as shown.

Figure 4-3: 4th-Order Test Circuit (with Delay) with Driver Circuit and Receiver Circuits Attached

The resulting time-domain output waveforms obtained from SPICE simulation of the circuit depicted in Figure 4-3 are displayed in Figure 4-4. Here the signal waveform 𝑣𝑖𝑛𝑡𝑒𝑟(𝑡) represents the driver input waveform, which is a perfect square- and pulse-type

signal. The node 𝑣_{𝑖𝑛𝑝𝑢𝑡}(𝑡) represents the driver output waveform, which is distorted due to the loading of the interconnect plus its own load and the associated reflections. The node labeled 𝑣_𝑜𝑢𝑡(𝑡) is the voltage at the output of the interconnect, at the input to the receiver load circuit. Note that the driver output waveform 𝑣_{𝑖𝑛𝑝𝑢𝑡}(𝑡) can also be considered to be the input waveform to the interconnect circuit, and that it is significantly different than the ideal pulse input of 𝑣_{𝑖𝑛𝑡𝑒𝑟}(𝑡). In subsequent chapters, at times it will be convenient to excite the various interconnect models obtained using different methods with the 𝑣_{𝑖𝑛𝑝𝑢𝑡}(𝑡) signal, so that the resulting output can be compared directly with that

1 nH 100 mΩ 2 nH 200 mΩ 1 pF Zo=50 Ω, Td=172 ps/inch 1.5 pF length=5.0 in. (12.7 cm) Lossy RLGC model 50 Ω 50 Ω vinter(t) vinput(t) v_out(t)

Figure 4-4: Time-Domain Output Waveforms for the 4th-Order Test Circuit (with Delay)

4.3 Creating a Frequency Transfer Function Model for the 4th-Order Test Circuit