In this section the design of a tapped-resonator oscillator is discussed. The first thing to be done now is to derive the optimum tap factor. Therefore equation (5.63) is rewritten with replaced by to account for the impedance transformation resulting from the tapping:
As the resonator impedance is changed, the optimum collector current will also change. It is given by:
In Section 5.5.1 it was shown that the output current of the resonator reduces proportionally with an increasing tap factor. Therefore resistor has to be made proportional to the tap factor in order to remain at the same voltage level at the output of the oscillator. Thus:
where is the value of without tapping; for this example. As the resonator voltage also depends on the tap factor (the output current is assumed to be given), the optimum tap factor has to be found from the maximization of the CNR and not from the minimization of the equivalent input noise voltage. Thus the function to be maximized is:
where is the input voltage of the tapped resonator and is the input voltage of the non-tapped resonator, which is independent of the tap factor.
This expression, normalized to the maximum CNR, is plotted in figure 5.27. As clearly follows from the figure, there is an optimum for which the CNR is only 15 % away from the maximum attainable CNR.
5.7. DESIGN EXAMPLES 147
From maximizing equation (5.75) the following expression is found for the optimal tap factor,
This equation holds when the following constraints are fulfilled: and
In contrast to the optimum tap factor which was found in Section 5.5.3, the optimum tap factor found here is a single value and not a range of values. This is because the noise power of resistor reduces proportionally to only see the dotted line in figure 5.13. But, as the noise contribution of is relatively small, the maximum is relatively flat, see figure 5.27.
For this example the optimum tap factor is found to be:
This optimum tap factor is close to the quality factor of the resonator
and will result in a reduction of the effective Q to about 33 and the CNR would be halved. As the maximum is relatively flat, the is halved and the effective Q is now about 43, with a corresponding CNR degradation of 20 %. The power density of the equivalent noise voltage increases by only 1 %.
The tapped resonator and the active part are depicted in figure 5.28. The following values are used for the resonator capacitors (the inductor is kept the same):
148 CHAPTER 5. HARMONIC OSCILLATORS
resulting in a resonance frequency equal to:
Capacitor is used for compensating for the equivalent parallel capacitance of the tapped resonator. Its value is derived in Section 5.7.3.3.
The actual tap factor can be calculated from the two capacitances, which equals:
The resonator resistance at resonance is therefore:
5.7.3.1 Signal power
In order to have the same oscillator output voltage as the previous design (for the same inductor current), has to be equal to:
and thus the ratio of and to obtain the required input impedance has to be equal to:
in which the factor 2 accounts for the double input impedance to ensure startup.
5.7.3.2 Noise
The optimum collector current for the input stage follows from equation (5.73), which yields:
However, as the noise contribution of the active part is relatively small compared with the noise contributed by the resonator (the actual CNR is close to the maximum CNR), the collector bias current can be reduced in order to save power. A current of about showed to be convenient as it proved to give an acceptable HF behavior. At this collector current the CNR ratio is reduced by only 3 %.
The equivalent noise resistance calculated at and including equals:
5.7. DESIGN EXAMPLES 149
5.7.3.3 Bandwidth
Capacitor in figure 5.28 is required to cancel the equivalent parallel capac- itance of the tapped resonator, which is 36 pF (560 pF in series with 39 pF). To compensate exactly for this capacitance, has to be 0.3 pF. But, as the input impedance of the oscillator is to be designed with a double magnitude, also has to be twice as large, in order to cancel the capacitance at startup. The second stage of the active part is implemented by a differential pair, as it was for the previous design.
Again, and are studied for the frequency behavior of the input impedance. The loop, for which the input is left open, has a loop gain of about -24. This is considerably reduced in comparison to the previous oscillator. The main cause is the lower value of and the higher value of The loop consists of a phantom zero due to and This phantom zero is equivalent to a pole in the input impedance (for infinite loop gain), compensating for the parallel capacitance of the tapped resonator. Besides the phantom zero two poles are also found in the loop, one at -90 kHz and one at -29 MHz. These two poles are from the input and output stage, respectively, and they are split by the base-collector capacitance of As a result the closed loop pole is found at -1.2 MHz instead of the intended -2.1 MHz. The extra phase shift of the input impedance at the resonance frequency is about -30 degrees. This is acceptable for the moment5.
The positive loop, for which the input port is shorted, has a loop gain of about 4. Only the pole from is relevant, resulting in the input impedance in a zero at +6.4 MHz. It should be noted that by shorting the input, the local feedback caused by the base-collector capacitance is broken, and thus the poles of and are not split.
As will be seen in the next section, for implementing the limiter it is power efficient to have a higher value for consequently will also become higher. The final values for and are respectively, and
5.7.3.4 The limiter
For the limiter, the same configuration is used as for the previous example. When a transconductance in its linear region of is realized (which was the first choice), the tail current of the differential pair, see figure 5.25, should be Therefore the value of and the transconductance of the limiter in its linear region are doubled. For the noise this gives a negligible small increase whereas it is more advantageous for the bandwidth of the input impedance. Now the pole in the transfer comes closer to the phantom zero, and as a result the additional phase is reduced to -20 degrees.
5
To reduce the effect of the base-collector capacitance to a large extent, a current buffer could be used preceding the stage [14].
150 CHAPTER 5. HARMONIC OSCILLATORS
5.7.3.5 The total circuit
In figure 5.29 the total schematic of the oscillator is depicted. This circuit is also supplied from a 1.3 V supply voltage in order to be able to also use the local series feedback in the current sources. The oscillator consumes about
The circuit diagram closely resembles that of the other oscillator. A difference can be found at the level shift required for proper functioning of the limiter. It also uses a diode-connected transistor but now a resistor, is placed in series with the base terminal. This is necessary for compensating at the limiter input for the voltage drop which is found across and caused by the base current of Capacitor is required to obtain the correct limiter transconductance again at the frequency of oscillation.
From small-signal simulations the equivalent input noise voltage at and including still equals:
5.7. DESIGN EXAMPLES 151
reduction due to the excess loop gain of the oscillator is ignored here for the moment), which is much better than the other oscillator. Of course, due to the additional phase shifts a lower effective Q is found, which is however of the same order of magnitude as that of the other example. The extra degradation of the CNR may be expected due to the Q-degradation caused by the tapping, which is about 1 dB.