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distribution in the presence of traps has been widely recognised (4.1-3]; however, it is only recently that, with the advent of C-V simulation models, reconstruction of the experimentally determined profiles has been possible. The increasing interest in band- engineered multilayer structures initiated much of this work and has led to a considerable degree of success in matching simulations to experimentally determined profiles [4.4-6]. However, the complexity of the profiles requires care in interpretation; certain trap distributions can, in particular situations, give rise to features in the apparent free carrier profiles not unlike the accumulation and depletion attributed to a heterojunction band offset [4.3, 4.7, 4.8].

The majority of the work on heterojunction band offsets determined from C-V work has been carried out in the III-V material system. Despite the maturity of this research area, discrepancies and anomalies exist in published results and there would appear to be some question as to the interpretation of results presented in particular cases. Kazmierski et al. [4.8] investigated the GalnAs/InP heterointerface; the dramatic changes observed in shape and position of the experimentally observed peak in the carrier profile as temperature was reduced were considered the result of interfacial trap response alone. Of note is the dramatic increase/decrease in extracted interface charge density/conduction band offset around the transition temperature at which the changes occur. Similar observations have been made by other workers but with different physical interpretations. Ogura et al. [4.9] found the same trends in extracted interface charge density/conduction band offset Fig 4.1a in InGaAs/InP as a result of changes in the carrier profile with temperature Fig 4. lb; however, in this case, the reduction in device capacitance at the transition temperature is considered in terms of the p + -n junction depletion capacitance in series with the capacitance associated with the heterojunction. The heterojunction capacitance is thought to vary as a consequence of trap filling at the heterojunction; whilst this explains the effect of reducing the heterojunction capacitance at the ubiquitous transition temperature (in this case = 160K), it ignores the presence of lower concentrations of the same deep level near the p + -n junction and their response at the measurement frequency. Interestingly, the transition from the LF to the HF regime occurs at approximately 160K; thus, this deep level will affect the measured capacitance for T£160K, as is shown for all reverse biases, and could explain the change in shape and position of the experimentally determined carrier profile. Whilst this does not eliminate the possible effect of a changing heterojunction capacitance, it does illustrate the care needed in interpretation of such measurements in the presence of traps. Work by Forrest et al. [4.10] again revealed the dramatic change in extracted parameters around 150K for the Ino.53Gao.4 7As/InP heterointerface; however, the change in shape and position of the carrier profile as temperature was reduced through this transition at 150K was not observed, despite similar trap

Fig 4. la Temperature dependence of the extracted interface charge density and conduction band offset for an InGaAs/InP heterostructure (after [4.9]).

Fig 4.1b Apparent free carrier distributions from which values extracted in Fig 4. la were obtained.

distributions to Ogura et al. The shift to lower temperature of this transition for a lower measurement frequency suggested some change in trap response, although this was not discussed; the physical significance of the reduction in conduction band offset was considered to be due to trap filling at low temperature, distorting the band structure and removing the effective band offset.

Work by t'Hooft et al. [4.11] considered the influence of dopant depth in the heterojunction region - reduced dopant ionisation as a consequence of the band bending would result in smaller degrees of accumulation and depletion in the vicinity of the heterojunction, resulting in the band offset being underestimated. Similar effects would occur for compensation of the shallow dopants since fewer free charge carriers are available in the heterojunction region.

Leu et al. [4.12] set out to investigate the possible distortion to heterojunction free carrier profiles in the presence of traps via simulations; this very thorough work provides amended equations from the analysis of Kroemer et al. [4.13] for the determination of trap density and conduction band offset in the presence of deep and shallow traps. The variation of the conduction band offset and interface charge density as a function of temperature/measurement frequency are discussed; it is proposed that the most accurate values of the conduction band offset are obtained within the low frequency or high temperature measurement regime. Part of the work presented later uses the simulation program [4.7] to determine the validity and applicability of their results in the Si and Si/Sij_xGex/Si material system investigated here. Further work by Leu et al. [4.14] considered the correction necessary to determine the conduction band offset for asymmetric trap distributions at the heterojunction with different doping levels either side of, and error in the actual position of, the heterojunction.

The relation between interface charge and bulk trap distributions, according to source purity and lattice mismatch, have also been investigated; once again, one must be aware that the distortion occurring to the free carrier distributions will ultimately affect the validity of the extracted interface charge density. Lee et al. [4.15] report low interface charge densities for the InQ.53^30.4 7As/InP heterointerface, independent of

measurement temperature and lattice mismatch. Carrier profiles show clear accumulation and depletion features over the entire measurement range of temperatures, in contrast to previous results [4.10]. No electrical activity is considered associated with the lattice mismatch whilst it is clear that the use of high purity In source material reduced the interfacial charge. Similarly, work by Whitney et al. [4.16] showed no relation between lattice misfit and interfacial charge for the Ino.5 3GaQ 47As/InP heterointerface - however, changes in shape and position of the carrier profile were observed as a function of temperature. Deep level distributions showed a peak towards the interface, suggesting a strong correlation to the interface charge. This was also suggested by Okumura et al. [4.17]; however, unless the exact nature of traps ie. donor or acceptor-like is determined, this apparent relation between interface charge and trap distribution is meaningless. Fixed charge is bias and temperature independent and will not be detected by spectroscopic techniques like DLTS; only interfacial traps with a variable occupancy will be detected by both DLTS and as an extracted interfacial charge via numerical integration of the carrier profile. Note that the extracted interface charge density will vary as a consequence of this, depending on the possible distortions that will occur to the heterojunction accumulation and depletion features in the presence of variable occupancy traps. In contrast, Morii et al. [4.4] found the interface charge density increased with increasing Al content for the AlxG ai.xP/GaP heterointerface and attributed it to the greater degree of lattice mismatch between the alloy layers. Similar conclusions were made by Ogura et al. [4.9] with both deep level and interface charge density increasing for increasing mismatch between InGaAs and InP.

Finally, only a few brief reports have been made regarding the use of the C-V technique to determine band offsets and interface charge densities in the Si/Si i_xGex/Si system. Denhoff et al. [4.18] found only approximate agreement between theoretically predicted and experimentally determined conduction band-offsets, with considerable error coming from the non-uniform bulk doping levels either side of the heterojunction. Tatsumi et al. [4.19] reported a valence band offset of 0 .18eV for x = 0 .3 and interface charge densities up to 3x10^ cm‘2 for x= 0.4 Ge composition layers, directly relating

the latter electrical activity to interfacial misfit dislocations; no apparent free carrier profiles were presented, so the accuracy of these results is unknown.

The ease and simplicity of heterojunction band offset and interface charge density extraction from the apparent free carrier distributions make C-V profiling a very powerful characterisation technique. However, care is needed in the interpretation of the results if traps are present; simulation programs can provide an assessment of the technique and validity of the experimentally determined parameters in such circumstances.