Raspberry pi

Step 2 Run DSP CLK/LST CLK to check whether the clock source is correct. If not, run MOD CLKSRC to modify the clock source.

Step 3 Run DSP CLK/LST CLK to check whether the work mode of the clock is correct. If not, run MOD CLK to modify the work mode.

Step 4 If the line clock is selected as the clock source, run DSP CLK/LST CLK to check whether the line clock configuration is correct. If not, run SET LINECLK to modify the line clock configuration.

----End

3.7 Cases of Clock System Faults

This describes the clock system faults such as internal clock faults and clock source faults in symptoms, causes, and troubleshooting. Clock system faults result in failure of service connection and interconnection with peer devices. Therefore, a normal clock system is essential for running of the UMG8900.

3.7.1 Clock Source Loss

This describes the symptoms, causes, and troubleshooting of clock source loss. The

UMG8900 uses the internal clock system if the external clock source is lost; however, using the internal clock oscillator for a long time results in noise or link disconnection in calls. The board clock faults usually occur during routine operation and maintenance of the UMG8900, service board failure, and clock distribution cable failure.

3.7.2 Board Clock Anomaly

This describes the symptoms, causes, and troubleshooting of board clock anomaly. Board clock anomaly means that the service board fails to provide services due to abnormal clock signals.

3.7.1 Clock Source Loss

This describes the symptoms, causes, and troubleshooting of clock source loss. The

UMG8900 uses the internal clock system if the external clock source is lost; however, using the internal clock oscillator for a long time results in noise or link disconnection in calls. The board clock faults usually occur during routine operation and maintenance of the UMG8900, service board failure, and clock distribution cable failure.

Symptoms

l An alarm related to clock source loss occurs on the alarm management system.

l The UMG8900 fails to provide time division multiplexing (TDM) services, and call interruption or signaling link disconnection occurs.

Causes

l The clock reference source is lost.

l The distribution cable between the clock source and the OMU is disconnected.

l The clock subboard is faulty.

Troubleshooting

1. Check clock related alarms and the alarm information on the alarm management system.

Clear the fault based on the alarm handling recommendations.

2. Contact the upper-level clock maintenance personnel to determine whether the upper-level clock source is normal.

3. For different clock sources, perform the following:

l Check whether the clock interface or E1/T1 trunk cable providing line clock is faulty.

If yes, replace the interface or trunk cable.

l Check whether the clock cable to the building integrated timing supply (BITS) clock is normal. If not, inform the peer office for handling.

4. Replace the clock subboard if it is faulty.

3.7.2 Board Clock Anomaly

This describes the symptoms, causes, and troubleshooting of board clock anomaly. Board clock anomaly means that the service board fails to provide services due to abnormal clock signals.

Symptoms

l An alarm for clock anomaly occurs on the alarm management system.

l Frame error or slip occurs to the OMU, the VPU fails to provide services, and noise or call loss occurs.

Causes

l The software version of the OMU is incorrect.

l The phase lock status of the clock subboard is incorrect.

l The VPU requiring clock works improperly.

Troubleshooting

1. Run LST BRDVER to check whether the software version of the VPU or the OMU is correct. If not, run LOD TOBP to load the software again.

2. Run DSP CLK to check whether the clock subboard is in the tracing phase lock status.

If not, run DSP CLK to check whether the reference source is normal. If not, clear the fault of the reference source.

3. If the clock subboard is normal but the clock of the VPU is abnormal, check whether the board is inserted in the correct slot. If not, pull out and then insert the board.

4 Clearing Interconnection Faults

About This Chapter

This describes the methods to clear interconnection faults. In networking applications, the UMG8900 may fail to interconnect with other network devices due to inconsistent settings of interface protocol parameters, data configuration error, abnormal network communication, interface failure, or peer device failure.

4.1 Fault Symptoms and Causes

This describes the symptoms and causes of interconnection faults.

4.2 Clearing H.248 Signaling Link Faults

This describes the methods to clear H.248 signaling link faults.

4.3 Clearing TDM Bearer and Signaling Transfer Faults

This describes the methods to clear time division multiplexing (TDM) bearer and signaling transfer faults.

4.4 Clearing IP Bearer Faults

This describes the methods to clear Internet Protocol (IP) bearer faults.

4.5 Clearing R2 Signaling Faults

This describes the methods to clear R2 signaling adaptation and transfer faults.

4.6 Cases of H.248 Signaling Link Faults

This describes the H.248 signaling link faults in symptoms, causes, and troubleshooting.

4.7 Cases of Signaling Transfer Faults

This describes the signaling transfer faults in symptoms, causes, and troubleshooting.

4.8 Cases of R2 Signaling Link Faults

This describes the R2 signaling link faults in symptoms, causes, and troubleshooting.

4.1 Fault Symptoms and Causes

This describes the symptoms and causes of interconnection faults.