Reactividad de la ciclooxigenasa 2 Simultáneamente al incremento en la reactividad de GFAP y OX-42 por efecto de la isquemia cerebral, se aumentó

Shared-memory processing environments are created by using groups of microprocessors which are able to access global shared memory via some interconnect. A key driving factor in the evolution of shared-memory multiprocessors was the observation that multiple levels of cache reduced the memory bandwidth requirements of each processor [99], allowing for multiple processors to use the same memory bus [113]. Introduction of caches into multiprocessor systems introduces two problems namely, (a) how does a processor know when a cacheline of interest to that processor is being used by another processor and (b) what a processor can infer about operations of a remote processor by observing the ordering of data reads and writes of the remote processor to main memory.

Problem (a) is addressed by a cache coherency scheme and problem (b) relates to the particular memory consistency model which has been implemented.

Cache coherency is defined by Jacob [131] “In the presence of a cache, reads and writes behave (to a first order) no differently that if the cache were not present”. As a cache is interposed between a CPU and memory it needs to ensure the processors’ view of memory is consistent with respect to data being cached i.e. data written to in a cache is guaranteed to be committed to memory and thus visible to all other processors. To enforce cache consistency, a cache coherency policy is defined which ensures that there is one globally unique, well-defined value associated with any given memory location.

A memory consistency model for a shared-memory multiprocessing system, ”is a formal specification of how the memory system will appear to the programmer” [6]. The mem- ory consistency model determines how a store operation in one thread of execution is made visible to the load operation of another thread, as well as implications about other load and store operations in both threads. All modern microprocessors implement some variation of a relaxed consistency model which allows for reads and writes to complete out-of-order, but also provides synchronization primitives to enforce ordering between multiple threads of ex- ecution [113]. This involves the use of hardware memory control and atomicity preserving operations such as: fenceon the x86 ISA,syncon the POWER ISA, andmembaron the SPARC ISA.

2.1.4.1 Cache Coherency Protocols

A cache coherency protocol enables for the physical implementation of cache consistency. Consistency needs to be maintained with the backing store as well as with other clients in a multi-processor setup. In single processor environments the write-back and write-through policies ensure the cache is consistent with its backing store, but in a multi-processor setup a

Figure 2.3: The MOESI Protocol states and transition conditions. If, for a given cacheline, a processor experiences a cache-miss a probe message is sent to other caches to obtain the required cacheline. From [5].

hardware coherence mechanism must be used. The MESI [124] and MOESI protocols are two examples of widely used coherency mechanisms. The MOESI protocol [270] is of interest in this thesis as it is implemented by two of the platforms used in this thesis, for which more details are presented in Section 2.1.7. Every cacheline is tagged using state bits to represent its most current state as part of the coherency protocol, in effect the coherency protocol is a per cacheline state-machine allowing the processor to implement cache consistency.

The MOESI protocol, shown in Figure 2.3, has the following states: Modified, Owned, Exclusive,Shared andInvalid –

Invalid Cachelines marked as invalid do not hold valid copies of data. All cacheline entries in the cache start off in the invalid state. Cachelines can also enter an invalid state once invalidated i.e. it transitions from one of the other states. Valid data for a cacheline resides either in main memory or in another processor’s cache.

Exclusive A cacheline in the exclusive state is exclusive to that particular cache i.e. it is the most current copy of the cacheline and is not in any other cache. Read misses, if serviced from memory cause cache lines to be marked as Exclusive as these cachelines are newly fetched directly from memory.

made modifications to that line i.e. if the cache gets a write hit. Future write hits will set the cache line in the Modified state. If the cacheline needs to be evicted, it is transitioned from the Modified state into Invalid.

Shared A Shared cacheline is one which has not been modified and is in cache, but could exist in another processor’s cache. A read-miss on a Modified cacheline will lead to a transition into the Shared state. A read-miss response from another cache will also cause the cacheline state to transition to Shared.

Owned A Modified cacheline can transition to the Owned state when the cache forwards the cacheline to another requesting cache, thus by-passing the backing store. The Owned state allows for a cacheline to be replicated to other caches (which hold it in the Shared state). The cache that owns the cacheline is permitted to modify Owned lines only.