ACTION 1: Open the script char_worst.tcl in the scripts directory. The purpose of each section is explained in the comment line:
set WORK_DIR [pwd]
set IN_DIR ${WORK_DIR}/data set OUT_DIR ${WORK_DIR}/out set SCRIPTS_DIR ${WORK_DIR}/scripts
# specify names of power and ground net and their respective voltage
# names are from netlist of cells set_vdd VDD 1.08
set_gnd VSS 0.00
# specify temperature and default voltage
# these values go into operating_conditions group in .lib file set_operating_condition -voltage 1.08 -temp 125
# source template for cells source $SCRIPTS_DIR/template.tcl
# specify cell list for characterization and
# override cell list read from template set cells { \
NOR3X1c \ }
# specify spice model (worst (SS) corner)
# spice model file must be in absolute directory set spice "${IN_DIR}/model_ss"
# create list of spice netlist for all cells foreach cell $cells {
lappend spice "${IN_DIR}/${cell}.spx"
}
# specify directory for all spice simulation related files to be saved set_var extsim_deck_dir ${OUT_DIR}/decks_SLOW
# save all SPICE decks and listings for successful simulations set_var extsim_save_passed all
# save all SPICE decks and listings for failing simulations set_var extsim_save_failed all
# include spice model in spide deck using ".inc/include" constructs
#set_var extsim_model_include "${IN_DIR}/model_ss"
# set this variable to 0 so that cell netlist file is not flattened
# in the netlist in the generated spice and
# .inc SPICE command is used to load cell netlist file
# when define_leafcell command exists.
set_var extsim_flatten_netlist 0
define_leafcell -type pmos {g45p1svt}
# read spice model and netlist read_spice -format spectre $spice
# characterize cells using spectre simulator char_library -cells $cells -extsim spectre
# write Liberate internal database into file for later use.
write_ldb ${OUT_DIR}/ldb.ldb
# write lib consisting of NLDM timing and power
write_library -cells $cells -user_data $USER_DATA -overwrite -filename
${OUT_DIR}/customlogic_worst.lib customlogic_worst
To summarize, the following inputs files are needed to run the characterization:
1) TCL command file to run Liberate 2) Template file
3) Spice model files of each corner
4) Extracted spice netlist for the cells to be characterized
5) User data attribute file if including the additional attributes and overriding the attributes in the generated .lib file are desired
Note: A NLDM (Non Linear Delay Model) timing library has been generated in this case. Liberate also supports the ECSM (Effective Current Source Model) and CCS (composite current source) models.
ACTION 2: Run Liberate to generate a timing library for the worst (slowest) delay corner. In the UNIX command line, type:
% liberate scripts/char_worst.tcl |& tee char_worst.log
Liberate will generate a timing library, customlogic_worst.lib, in the out directory.
Open up this library file and search for the area. You will see the following statement:
cell (NOR3X1c) { area : 0;
cell_leakage_power : 0.0461599;
leakage_power () {
Apparently, it indicates that the cell has 0 area. This is because, by characterization, you can only calculate values that can come through simulations. But for the attributes like the area or footprint (not shown in this workshop), these pieces of information do not come out from characterization. To override the attribute or to include additional attribute, you need to create a file that specifies the attribute and uses the –user_data option of write_library to do the job. This file is already created in the scripts directory and is named user_data_worst.lib.
ACTION 3: Open up user_data_worst.lib in the scripts directory:
rail_connection( VDD, RAIL_VDD );
rail_connection( VSS, RAIL_VSS );
pin(A) {
input_signal_level : RAIL_VDD;
}
pin(Y) {
output_signal_level : RAIL_VDD;
}
pin(B) {
input_signal_level : RAIL_VDD;
}
pin(C) {
input_signal_level : RAIL_VDD;
} } }
Assume the area to be 1.71 unit (copy from the NOR3X1 cell in the existing timing library file). You want to add additional attribute to the library and the cell. All this information is specified in this file.
ACTION 4: Open up the script, write_lib_worst.tcl, in the scripts directory to view the content. This file will be used to run with Liberate to update the attributes.
set WORK_DIR [pwd]
# write Liberate internal database into file for later use.
read_ldb ${OUT_DIR}/worst_ldb.ldb
# for updating library and cell attributes with user data library file set USER_DATA ${SCRIPTS_DIR}/user_data_worst.lib
write_library -cells $cells -user_data $USER_DATA -overwrite -filename
${OUT_DIR}/customlogic_worst.lib customlogic_worst
# write datasheet
exec mkdir -p ${OUT_DIR}/DATASHEET
write_datasheet format text conditional dir ${OUT_DIR}/DATASHEET cells $cells -filename ${OUT_DIR}/DATASHEET/customlogic_worst.txt customlogic_worst
# writing verilog models
write_verilog -cells $cells ${OUT_DIR}/verilog.v
You have run the characterization in the previous step and saved the characterized database as
worst_ldb.ldb. In this script, you only reload the saved database, worst_ldb.ldb, and write the timing library again with the –user_data option. In this script, you also instruct Liberate to write out the datasheet and Verilog file for this cell.
ACTION 5: Run Liberate to generate a timing library for the worst (slowest) delay corner with the user data attributes included. In the UNIX command line, type:
% liberate scripts/write_lib_worst.tcl |& tee write_lib_worst.log
You might want to open up again the timing library file, customlogic_worst.lib, and spot the difference.
For example, the NOR3X1c cell has more attributes now as shown here:
cell (NOR3X1c) {
ACTION 6: Run Liberate to generate a timing library for the best (fastest) delay corner. In the UNIX command line, type:
% liberate scripts/char_best.tcl |& tee char_best.log
You might want to view the content of char_best.tcl. Most of the statements are similar to
char_worst.tcl. The key differences will be the operating_condition (voltages and temperate) and the spice model files.
set_operating_condition -voltage 1.32 -temp 0 set spice "${IN_DIR}/model_ff"
Note that, for the best corner, the same spice netlist file for NOR3X1c is being used. In this case, you will use the typical case and assume that the variation of the parasitic RC in the logic gate is negligible. For better accuracy, the different corners of the spice netlist file for the cells to be characterized should be used.
In this script, go ahead to write the timing library file with the user data attributes.
After the run, as a simple check, you might want to open up the timing library file for the fast corner, customlogic_best.lib, and verify the timing numbers are faster than that of customlogic_worst.lib.
For example, the cell_rise table of the NOR3X1c cell in customlogic_worst.lib is:
cell_rise (delay_template_7x7) {
For the same type of table in customlogic_best.lib, the values are:
cell_rise (delay_template_7x7) {