4.5 Recursos de las Empresas
4.5.4 Recursos Técnicos
interest, especially off-state voltage stress [156]. There are some explanations for this, such as hot- electron inducted trap formation [156], [308], [309] and electric-field induced defect formation in association with inverse piezoelectric effect in AlGaN/GaN [46], [151], [310]. During applications, sometimes the devices have to be kept at on state for a long time, in order to imitate the situation, electrical stress like we have discussed in section 2.5.2. Based on this idea, the electrical estability of the HEMT and MOS-HEMT with HfO2 after gate and drain electrical stress.
During the study, two kinds of electrical stress were carried out, one is off-state stress with voltage biased on the drain side, similar to those discussed in the literatures[311] and the other is voltage bias on the gate side, such as [309], [312]–[314].
The effects of gate stress
Long term off-state step stress was that voltage stress is applied to the gate side of the device, VGS
is stepped from -7 to -39 V, in -2 V steps; each stress lasts for 1800 s, and gate and drain were grounded. The gate step stress is similar to those reported in the literatures [148], [315], [316]. DC IV and transconductance measurements were conducted right after each stress step. The bias stress protocol is shown in Figure 7-1.
Figure 7-1 Gate stress protocol
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Figure 7-2 shows the change of IV curves of the devices and the ID,max and RON change with gate
stress voltage in the device. The changing trend of ID,max and RON shows that the decrease of the device
property starts at about -25 V, and the increase reaches to 100% at -35 V.
The transconductance curves of the devices are shown in Figure 7-3. The change of gm,max with stress
voltage are shown in Figure 7-3 (b). Similar to the change of ID,max, The gm,max has decreased by 22%
after -35 V stress.
Figure 7-3 (a) Change of transconductance curves with gate stress and (b) gm,max changes
during step-stress experiments
This voltage could be considered as a critical voltage, from which the device shows critical degradation [157], with decreased ID,max and gm,max, as already reported in previous publications [315].
(b) 0 -10 -20 -30 -40 0.0 0.2 0.4 0.6 IDS (A/m m)
Gate Stress Voltage (V)
0 4 8 12 16 20 RON ( mm )
Figure 7-2 (a) Change of IV curves with gate stress and (b) IDS and RON changes during step-
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There are several explanations for the existence of critical voltage, one is due to metal diffusion at the gate drain edge of the devices, which has been observed from TEM pictures in many previous discussions [148], [156], [137], [187], [315]. Other cause is the presence of O-Ga or O-Ni bondings during or after the electrical stress under the gate. Chien-Fong Lo et al. showed that Pt based gate shows improved critical voltage than the conventional Ni/Au gate [315]. Another relevant issues to be discussed have to do with the properties of the epilayer: one is that there will be a lot of crystallographic defects caused by inverse piezoelectric effect from high vertical electric field, mostly at the drain edge of the gate [148], [151], [153], [158]; the other is hot-electron-induced trap generation [317], [318].
The effects of drain stress
Long term off-state step stress was that Voltage stress is applied to the drain side of the device, VDS
is stepped from 13 to 39 V in 2 V step, while keeping VGS= -7 V, the device is stressed for 1800 s at each
voltage step. DC IV and transconductance measurements were conducted right after each stress step. Figure 7-2 shows the change in ID,max (drain current at VGS= 1 V and VDS= 7 V), RON, IG,OFF (gate current
at VGS= -6 V and VDS= 0.15 V) and gm,max as the stress proceeds. The drain bias stress protocol is shown
in Figure 7-4.
Figure 7-4 Drain stress protocol
GaN/AlGaN/GaN conventional HEMTs
The IV and transconductance of the conventional HEMTs during the drain stress are shown in Figure 7-5 . The changing trend of the ID,max, RON and gm,max are shown in Figure 7-6. Results show that there
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HEMTs, especially the gm,max decreased suddenly at drain gate voltage of 33 V. This voltage could be
considered as a critical voltage, from which on, the leakage current increase dramatically, causing devices degradation [157], similar to those have seen from previous publications [46], [151], [158].
Figure 7-5 (a) Change of IV curves with gate stress and (b) Change of IV curves with gate stress
In the conventional HEMTs of this case, diffusions occur among dislocations, accelerated by hot- electrons.With the increase of electrical stress voltage, inverse piezo-electric strain would occur, to further accelerate the electron diffusion in the device, causing an increase of gate leakage current and a decrease of dc electrical properties, as we have observed.
Regarding the gradual decrease of the DC behaviors of the devices, there are two possible explanations: one is due to the crystallographic defects caused by inverse piezoelectric effect from high vertical electric field at the drain edge of the gate [148], [151], [153], [158]; and the other is hot- electron-induced trap generation [317], [318].
Figure 7-6 (a) Change in normalized IDmax and RON and (b) gm,max Change during step-stress
experiments -5 0 5 10 15 20 25 30 35 40 45 50 0.2 0.4 0.6 0.8 1 1.2 Conv-HEMTs ID,ma x (V) /ID ,ma x (0 )
Drain Gate Voltage (V)
(a) 1 2 3 4 5 RON (V) /R ON (0 ) 0 5 10 15 20 25 30 35 40 45 50 60 80 100 120 140 Conv-HEMTs gm,ma x (m S/m m )
Drain Gate Voltage (V)
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HfO
2/GaN/AlGaN/GaN MOS-HEMTs
The IV and transconductance curves of the MOS-HEMTs during stress are shown in Figure 7-7. There is a decrease of 30% for the ID,max MOS-HEMTs with KOH cleaning. And the ID,max, RON and IG,OFF of both
MOS-HEMTs and the conventional HEMTs are shown in Figure 7-8. There is gradual degradation for the MOS-HEMTs, despite cleaning procedures, while for conventional HEMTs, there is a sudden degradation up to VDG=33 V, similar to those decrease of gm,max, as explained in the previous part. This
voltage is the critical voltage of the conventional HEMTs, from which on the leakage current increase dramatically, causing severe devices degradation [157], similar to those seen from previous publications [46], [151], [158].
Figure 7-7 (a) Change of IV curves with gate stress and (b) Change of IV curves with gate stress
There is no sudden decrease of gm,max or sudden increase of IG,OFF observed in the MOS-HEMTs
despite cleaning procedure. This is because the critical voltage of the MOS-HEMTs is higher than the maximum stress voltage we have applied during the experiments, suggesting the improving of critical voltage of MOS-HEMTs using HfO2 dielectric layer.
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Figure 7-8 (a) Change in normalized IDmax (left) and RON (right) in step-stress experiments for
three different stress conditions, (b) Change in the gate leakage current IGoff (gate current at
VDS = 0.15 V and VGS = −6 V) in the experiment
Another issue to discuss is the behaviours of the three kinds of MOS-HEMTs using different cleaning procedures. From the normalized ID,max, RON and gm,max change shown in Figure 7-8, almost no
difference in the RON change was observed. However, the ID,max of the MOS-HEMTs with only organic
cleaning showed more decrease than the ones with KOH cleaning. Therefore, the best case for all the electrical properties was the MOS-HEMTs with KOH cleaning.
Based on the observed behaviours, the HfO2 dielectric in between drain and source could help
inhibit the hot-electron and inverse piezo electric caused degradation in the devices.
Summary
In general, the effects of electrical stress on AlGaN/GaN conventional and MOS-HEMTs with HfO2
are discussed in this chapter. First, we have analyzed the gate step stress, experiments were done on the MOS-HEMTs with 0.5 M KOH cleaning. Results show that there is gradual decrease of ID,max and
gm,max, as well as gradual increase of RON in the devices. Besides, there is a gap in the gm,max after stress
of -27 V, which is the critical voltage of the MOS-HEMTs at the gate side. This can be explained in two aspects, one is the properties of the gate and the other is the properties of the heterostructures. For the first one, there might be gate metal diffusion or O-Ga and O-Ni bondings at the gate drain side. For the other aspect, there might be the crystallographic defects due to inverse piezoelectrical properties or hot electron induced traps.
Then, the effects of drain electrical stress on both conventional HEMTs and MOS-HEMTs were discussed. Firstly, the difference of the stress effects between conventional HEMTs and MOS-HEMTs
-5 0 5 10 15 20 25 30 35 40 45 50 0.2 0.4 0.6 0.8 1 1.2 Conv-HEMTs MOS-HEMTs (Organics) MOS-HEMTs (KOH) ID,ma x (V) /ID ,ma x (0 )
Drain Gate Voltage (V)
1 2 3 4 5 RON (V) /R ON (0 ) (a) 5 10 15 20 25 30 35 40 45 50 10-4 10-3 10-2 10-1 100 Conv-HEMTs MOS-HEMTs(Organics) MOS-HEMTs(KOH) IG,o ff (V) /IG,o ff (0 )
Drain Stress Voltage (V)
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are compared. Results show that there is critical point of gate drain voltage at about 33 V in the conventional HEMTs, which is not observed in the MOS-HEMTs. Different from the previous discussion before, this critical voltage mostly probably due to the properties of the heterostructure: the crystallographic defects due to inverse piezoelectrical properties or hot electron induced traps. This is not observed in the MOS-HEMTs, implying the improvements of the MOS-HEMTs with HfO2 dielectric
layers.
A short discussion about the comparison among the MOS-HEMTs with different cleaning procedures is given. The MOS-HEMTs with KOH cleaning have shown the best behavior among the three kinds of HEMTs.
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