La Red Unidos y el Plan Territorial para la Superación de la Pobreza Extrema

In addition to the baseline FEMB and ASIC designs discussed in Section 3.2.3, two other FEMB and ASIC options are currently under consideration. There is one official alternative design, the

SLAC nEXO three-chip CRYO ASIC, and one fallback option for the ADC ASIC, the Columbia

University ATLAS-style ADC ASIC. These options are described in Section 3.2.4.1 and Sec- tion 3.2.4.2, respectively.

3.2.4.1 nEXO CRYO ASIC

The SLAC CRYO ASIC differs from the baseline three-chip design in that it combines the functions of an analog preamplifier, ADC, and data serialization and transmission for 64 wire channels, into

a single chip. It is based on a design developed for the nEXO experiment5 and differs from it only

in the design of the preamplifier, which is modified to account for the higher capacitance of the DUNE SP module wires compared to the small pads of nEXO. The FEMBs constructed using this chip would use only two ASICs, compared to the 18 (eight FE, eight ADC and two COLDATA) needed in the baseline design. This drastic reduction in part count may significantly improve FEMB reliablity, reduce power, and reduce costs related to production and testing.

Figure 3.9 shows the overall architecture of the CRYO ASIC, which will be implemented in 130 nm CMOS. It comprises two identical, 32-channel blocks. The current signal from each wire is amplified

using a preamplifier with pole zero cancellation and an anti-alias fifth-order Bessel filter applied. Provisions are also made for injection of test pulses. Gain and peaking time are adjustable to values similar to those of the baseline design.

Figure 3.9: Overall architecture of the CRYO ASIC.

The ADC uses 8 MHz successive approximation registration (SAR), so that four input channels are multiplexed onto a single ADC. The data serialization and transmission block employs a custom 12b/14b encoder, so that 32 channels of 12-bit, 2 MHz data can be transmitted with a digital bandwidth of only 896 Mbps, which is significantly less than the required bandwidth of the baseline, which is 1.28 Gbps.

One key concern with mixed signal ASICs is the possibility of interference from the digital side causing noise on the very sensitive preamplifier. Fortunately, there are well established techniques for substrate isolation described in the literature [8], which have been successfully employed in previous ASICs produced by the SLAC group.

The infrastructure requirements for a CYRO ASIC-based system are similar to those of the baseline option. However, in most cases, somewhat fewer resources are needed:

• A single voltage is needed for the power supply. This is used to generate two supply voltages using internal voltage regulators.

• The output digital bandwidth on each of the four lines in an FEMB is 896 Mbps. This is lower than the baseline option due to the custom 12b/14b encoder of the CRYO chip. • The warm interface is different. Only a single clock is needed (56 MHz) and the configuration

The first prototype of the CRYO ASIC is in the final design and simulation stages. Simulation- based studies have already been performed; at 0.8 µs peaking time and an input capacitance of

200 pF (similar to that expected in the DUNE SP module), the ENC is approximately 500 e−.

This noise level is similar to that expected with the baseline FE and ADC ASIC design in LAr with the same input capacitance. Submission to the ASIC foundry is imminent and the first prototypes should be received by summer 2018. They will first be tested in an existing test stand at SLAC. Subsequent tests are planned for a small test TPC at Fermilab and on an APA in the ProtoDUNE-SP cold box; these test facilities are described in Section 3.5.2.

3.2.4.2 ATLAS ADC ASIC

An alternative ADC solution is to adapt the ADC chip under development for the ATLAS LAr calorimeter readout upgrade for the high luminosity LHC. The main ATLAS requirements are given in Table 3.3. Adapting the chip to the SP module needs would require doubling the number of channels per chip as well as adapting the output architecture. These are both relatively simple changes compared to the overall complexity of the chip.

Table 3.3: Performance requirements for the ATLAS-style ADC ASIC.

Parameter Specification

Channels/chip eight preferred, four minimum

Sampling Frequency 40 MHz

Dynamic Range 14 bits

Precision 11 ENOB

Power < 100 mW/channel at 40 MHz

Input 2 V differential

Output E-link interface operating at 640 Mbps

To achieve a 14 bit dynamic range, each analog channel is comprised of two main sections: a dynamic range enhancement (DRE) block that determines the most significant two bits of the 14 bit digital code, followed by a 12 bit SAR block. The input signal to the DRE block is sampled on two paths, one with unity gain and the other of gain four. A comparator determines which gain to use. The signal from the selected DRE gain is presented at the DRE output, which is connected to the input of the 12 bit SAR ADC block. The DRE design has been carefully optimized so that its output preserves the required 12 bit performance.

Following current state-of-the-art ADC development techniques, a two-stage SAR architecture is used, exploiting the high speed of the technology while maintaining the SAR input capacitance at a reasonable value. Since capacitor matching in this technology might not meet the precision required, the ADC will use bit redundancy, i.e., determine more bits than its actual output, and the redundant bits will be used to both calibrate the ADC and produce correct output codes. Such procedures are well understood and applied to both pipeline [10] and SAR [11] ADCs us- ing foreground or background calibration techniques. Details of the SAR design are shown in Figure 3.10.

Figure 3.10: Block diagram depicting the two-stage SAR design of the ATLAS ADC ASIC. An ADC test chip, dubbed COLUTA65V1, was designed and submitted for fabrication in May 2017 and received in September of 2017. The DRE and SAR blocks of the COLUTA65V1 were first tested independently. Measurements were made of the SAR precision using the sine-wave fast Fourier transform method. An effective number of bits (ENOB) of 11.6 bits at 20 MHz (after calibration) was obtained. Both DRE and SAR were successfully integrated with negligible degra- dation in performance. The COLUTA65V1 chip was also tested at 2 MHz and shown to work as designed, meeting the requirement for the SP module. Tests of an updated design in liquid nitro- gen are planned for spring 2018. Additional tests associated with meeting power requirements will be carried out if this ADC option is further pursued.