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The virtual and overlay architectures provide more flexibility. The designers should be able to debug their virtual architecture designs in-system, without detailed knowledge of the hardware’s limitations.

VCGRAs consist of a large number of processing elements (PEs), laid out in a grid pattern, and Virtual Channels (VCs), that are a communication network connecting the PEs. Each PE is a coarse-grained element (realized mainly using LUTs) and it is capable of computing incoming data and pass it on to the next PE, via an adjacent VC. The VCGRA is implemented using reconfigurable connec-tions, with the assistance of the PConf flow. A VCGRA needs to be changed when the application implemented on the FPGA needs to change or adapt. Since some of the VCGRA’s inputs are implemented based on the PConf tool flow, that means that the VCGRA needs to be changed/adapted infrequently, as the reconfiguration time is the bottleneck of these architectures. Hence, instead of implementing the VCGRA’s instruction inputs as regular inputs, with PConf these inputs are imple-mented as constants and the FPGA overlay is optimized for these constants [90], as it was analyzed in Chapter 2.

Academic works have leveraged FPGA overlays to improve their debugging methods. In debugging with the use of FPGA overlays, the authors have used mainly incremental compilation, to insert trace-buffers, after the design is mapped and finalized on the FPGA [31,32,61]. These tools support only academic FPGAs and they use the remaining FPGA logic to construct virtual routing networks for signal tracing and to add debugging circuitry. However, the size of the overlay and the amount of its resources and routing needed can make its construction challeng-ing and can affect the original design’s timchalleng-ing and critical path. Moreover, in the

above-mentioned methods, the researchers create overlays to assist the debugging process, without the possibility to debug the FPGA overlay itself.

4.1.2 Contribution

The proposed method combines the advantages of enhanced internal signal ob-servability and fast FPGA reconfiguration in one tool flow. It has four main parts:

a parsing and mapping step to create the VCGRA, a design step to add the debug-ging infrastructure incrementally, a parameterization step that is used in the case of virtual FPGA architectures in the DUT and an online step that adapts the debug-ging methodology to a target design. This approach has some benefits over other debugging methods:

• Extended internal observability: By integrating with the PConf approach, the designer can trace sets of signals fast, completing the debugging process within time constraints.

• Reduced area resources: By adding the debugging infrastructure on a higher-abstraction level (overlay architecture) and dynamically adapting the added on-chip memories, the extra resources are reduced.

• Automated tool: The designer has just to select the DUT and to run the flow to create the debugging infrastructure for the VCGRA in order to per-form signal tracing. Semi-automated interventions reassure that the DUT’s debugging hardware remains minimal and fully parameterized.

The main contribution in the debugging integration is the possibility of adding debugging hardware on a higher abstraction level. This is done when the appli-cation is transformed to a VCGRA. In this way, the signal tracing hardware is co-designed alongside the VCGRA. A netlist is generated that has integrated de-bugging functionality and can be adapted without affecting the VCGRA under test [80].

The contribution of this chapter is illustrated in Figure 4.1, where it can be visualized how it is connected with the rest of the thesis. It is shown how this chapter enhances the debugging step with a second overlay (VCGRA generation) and a more automated debugging process (SDA).

This technique integrates in-circuit debugging functionality in an FPGA over-lay. The added functionality enables the user to debug large designs mapped on FPGAs without significant area overhead. A realistic application is used in order to validate the feasibility of the debugging architecture. In the experiments sec-tion, an exploration of the area and runtime overhead is realized, to validate the scalability of the method and of the signal integration algorithms, while increas-ing the design size and decreasincreas-ing the size of the available FPGA resources. In

One FPGA-overlay level Two FPGA-overlay levels

PConf backbone Synthesis

In-Circuit Debugging with VCGRAs

Mapping

parameterized SDA netlist

Place & Route

Gate Rank SDA

VCGRA generation

VCGRA arch

Figure 4.1: Visualization of this chapter’s contribution

addition to the added functionality, the efficiency of the proposed tool is explored, for both academic and commercial FPGA architectures. Moreover, an on-the-fly adaptation of the debugging infrastructure is proposed, that achieves a balanced trade-off between area overhead, signal observability and compilation time.

This chapter analyzes how a second FPGA overlay can be applied on a specific overlay (VCGRA) architecture, in such a way that it will provide in-circuit debug-ging functionality and without altering the original design. First, parameterization of the internal signals of a given design under test, on a VCGRA level is proposed.

Then, signal compression of mutually exclusive signals (during runtime) is used to reduce the area overhead of the debugging circuitry, while increasing its flexibility.

The entire concept of debugging with FPGA overlays is applied for two different FPGA architectures. Thus, three contributions are made:

1. This chapter introduces FPGA overlay debugging methodologies in both academic and commercial FPGAs. Integration with state-of-the-art FPGA-design platforms is also presented, that allows researchers to map their de-signs in commercial FPGAs.

2. The unique architecture of the VCGRAs is leveraged, alongside its layer-by-layer data path, to selectively add debugging functionality in such a way that with minimal monitoring, it can perform on-silicon debug, where the designer can observe the results and adapt the VCGRA. Both parameterized configurations and conventional dynamic reconfigurations are used, as well as an AXI-wrapper that packages the VCGRA-SDA system. This is intro-duced as a third-party IP. The creation of an IP will allow real applications of the proposed system. This method can be used by integrating the IP in a design.

3. A tool flow that applies the above-mentioned techniques to a given design automatically. A complete tool that co-creates the VCGRA and the debug-ging circuitry is provided, where the same automations that can create a VC-GRA can generate an SDA as well. A second layer is created, that provides dynamic signal tracing in the VCGRA. The tool co-designs the VCGRA and the SDA in such a way that they are interconnected. The tool is integrated in the Vivado tool flow and it can rapidly generate (offline) the files needed for the tool to create the IP and install both the VCGRA and the SDA.

The remainder of this chapter is organized as follows: Section 4.2 presents the proposed two-overlay technique and its architectures and Section 4.3 presents the adapted design flows that support them. Section 4.4 describes the experiments that were conducted and their results, followed by the Conclusion in Section 4.5.