Rentabilidad de la Inversión

The MIPS architecture provides several groups of instructions including arithmetic, logi- cal, shift, and branch. In this section we look at some sample instructions so that we can

write meaningful assembly language programs. Later chapters give a more complete and detailed discussion of these instructions.

Arithmetic Instructions

The MIPS instruction set has four arithmetic instruction types to perform addition, sub- traction, multiplication, and division. Here we discuss the first two types of instructions. Addition The basic addition instruction

add Rdest,Rsrc1,Rsrc2

adds the contents ofRsrc1andRsrc2and stores the result inRdest. The numbers are treated as signed integers. In case of an overflow, an overflow exception is generated. We can useadduif no overflow exception is needed. Except for this, there is no difference between theaddandadduinstructions.

For convenience, assembler provides a pseudoinstruction that can take either a register or an immediate value as the second source operand. The format is

add† Rdest,Rsrc1,Src2

where Src2 can be a 16-bit immediate value or a register. We can use addu† if the overflow exception is not needed.

Subtraction The subtract instruction

sub Rdest,Rsrc1,Rsrc2

subtracts the contents of Rsrc2 from Rsrc1 (i.e., Rsrc1 − Rsrc2). The result is stored inRdest. The contents of the two source registers are treated as signed numbers and an integer overflow exception is generated. We can usesubuif this exception is not required.

Logical Instructions

The MIPS instruction set supports several logical instructions. In this section we discuss the two basic instructions: andand or. Chapter 15 gives a complete discussion of the logical instructions.

These instructions operate on bit-by-bit basis. The truth tables for these logical oper- ators are given in Table 10.4. The format of these instructions is similar to that of theadd andsubinstructions, as shown here:

and Rdest,Rsrc1,Rsrc2

This instruction performs bitwise andon the content of theRsrc1 and Rsrc2 regis- ters and stores the result in theRdestregister. For example, the following sequence of instructions

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Table 10.4Truth tables for theandandorlogical operations

andoperation oroperation

Input bits Output bit Input bits Output bit source1 source2 destination source1 source2 destination

0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 1 li $t0,0x55 li $t1,0xAA and $t2,$t1,$t0

leaves zero in the$t2register.

The processor does not support the logical not operation. However, this missing logical operation is supported by a pseudoinstruction. Thenotpseudoinstruction takes a source operand and a destination operand, as shown below:

not† Rdest,Rsrc

It performs bitwise logicalnotof theRsrcoperand and stores the result in theRdest register.

Shift Instructions

Both left-shift and right-shift instructions are available to facilitate bit operations. The number of bit positions to be shifted (i.e., shift count) can be specified as an immediate five-bit value or via a register. If a register is used, only the least significant five bits are used as the shift count.

The basic left-shift instructionsll(shift left logical)

sll Rdest,Rsrc,count

shifts the contents ofRsrcleft bycountbit positions and stores the result in Rdest. When shifting left, vacated bits on the right are filled with zeros, as shown below:

0 1 2 4 28 29 30 31 0

The right-shift instructionsrl(shift right logical) has a similar format but shifts the bits in the opposite direction, as shown below:

0 1 2 4 28 29 30 31 0

As with thesllinstruction, the vacated bits are replaced by zeros. These shifts are called logical shifts. In Chapter 15 we show another category of shifts called arithmetic shifts when dealing with the right-shifts.

Branch Instructions

The MIPS instruction set provides several instructions to alter flow control. These include both unconditional and conditional branch instructions. Here we discuss a few of these instructions. The unconditional branch instruction

b† target

transfers control totargetunconditionally. As indicated here, this is a pseudoinstruc- tion. Here is an example that illustrates the use of the unconditional branch instruction:

li $t0,50

repeat:

add $t1,$t1,1

sub $t0,$t0,1

b repeat

As written here, it is an infinite loop! We modify this code later to terminate the loop after 50 iterations. For this, we need a conditional branch instruction.

There are several conditional branch instructions. Recall from our discussion in Chap- ter 2 (on page 24) that conditional branch can be done in one of two ways: set-then-jump or test-and-jump. The MIPS instruction set provides several instructions to perform test- and-jump conditional branching. For example, the branch on not equal instruction

bne Rsrc1,Rsrc2,target

tests the contents of the two registersRsrc1andRsrc2for equality and transfers control totargetifRsrc1=Rsrc2. If we assume that the numbers to be compared are in registers$t0and$t1, we can write the branch instruction as

bne $t1,$t0,target

The condition tested can be changed to “equal to”, “less than”, and so on. For example, the conditional branch instruction

blt Rsrc1,Rsrc2,target

compares the contents ofRsrc1andRsrc2and transfers control totargetifRsrc1 < Rsrc2. In comparing the contents of these two registers, they are treated as signed numbers. For example, if$t1= 5and$t0=−1, the instruction

172 Guide to RISC Processors

bne $t0,$t1,target

transfers control to targetas$t0<$t1. However, if we treat the contents of these registers as unsigned, the condition $t0_< $t1is not true as $t0contains all 1 bits (that’s how −1 is stored in 2’s complement notation). If you want to treat the number as unsigned, simply append the mnemonic with auas inbltu. For a complete list of conditional branch instructions, see Table 14.2.

The MIPS instruction set also provides another group of conditional branch instruc- tions that compare the value of a register to zero. For example, consider the beqzin- struction shown below:

bnez Rsrc,target

This instruction transfers control totarget if the value ofRsrcis not equal to zero. Using this instruction, we can rewrite the previous infinite loop code fragment as

li $t0,50

repeat:

add $t1,$t1,1

sub $t0,$t0,1

bnez $t0,repeat

to terminate after 50 iterations.

We can also use other relationships such as “less then”, “greater than” and so on. A complete list of these conditional branch instructions is given in Table 14.3 on page 250.