Requerimientos informáticos.

Since crosstalk is prevalent in virtually every aspect of a design, and its effects can be quite detrimental to system performance, it is useful to present some general guidelines to help reduce crosstalk. It should be noted, however, that all these guidelines will have adverse effects on the routability of the printed

Figure 3.19: Dimensions that influence crosstalk.

circuit board. Since most circuit board designs are required to fit some predefined aspect ratio (i.e., a motherboard may be required to fit in a standard ATX chassis), a certain degree of crosstalk impact is inevitable. The following guidelines, however, will help the designer limit the negative impact of crosstalk. Refer to Figure 3.19 when reading the following list.

1. Widen the spacing S between the lines as much as routing restrictions will allow. 2. Design the transmission line so that the conductor is as close to the ground plane as

possible (i.e., minimize H) while achieving the target impedance of the design. This will couple the transmission line tightly to the ground plane and less to adjacent signals.

3. Use differential routing techniques for critical nets, such as the system clock if system design allows.

4. If there is significant coupling between signals on different layers (such as layers M3

and M4), route them orthogonal to each other.

5. If possible, route the signals on a stripline layer or as an embedded microstrip to eliminate velocity variations.

6. Minimize parallel run lengths between signals. Route with short parallel sections and minimize long coupled sections between nets.

7. Place the components on the board to minimize congestion of traces.

8. Use slower edge rates. This, however, should be done with extreme caution. There are several negative consequences associated with using slow edge rates.

3.10. ADDITIONAL EXAMPLES

This example will build on the additional example in Chapter 2 and incorporate the effects of crosstalk into the high-speed bus example. Crosstalk often places severe limits on system performance, so it is important to understand the concepts presented in this chapter.

3.10.1. Problem

Assume that two components, U1 and U2, need to communicate with each other via an 8-bit-

wide high-speed digital bus. The components are mounted on a standard four-layer motherboard with the stackup shown in Figure 3.20. The driving buffers on component U1

have an impedance of 30 Ω and a swing of 0 to 2 V. The traces on the printed circuit board (PCB) are required to be 5 in. long with center-to-center spacing of 15 mils and impedance 50 Ω (ignoring crosstalk). The relative dielectric constant of the board (εr) is 4.0, the

transmission line is assumed to be a perfect conductor, and the receiver capacitance is small enough to be ignored. Figure 3.21 depicts the circuit topology.

Figure 3.20: Cross section of PCB board used in the example.

Figure 3.21: Circuit topology.

The transmission line parasitics are mutual inductance = 0.54 nH/in. mutual capacitance = 0.079 pF/in.

self-inductance = 7.13 nH/in. (from the Chapter 2 example) self-capacitance = 2.85 pF/in. (from the Chapter 2 example)

3.10.2. Goals

1. Determine the maximum impedance variation on the transmission lines due to crosstalk.

2. Determine the maximum velocity difference due to crosstalk.

3. Assuming that the input buffers at component U2 will switch at 1.0 V, determine if the

3.10.3. Determining the Maximum Crosstalk-Induced Impedance

and Velocity Swing

As discussed in Section 3.6.2, the equivalent impedance of a transmission line in a coupled system is dependent on the switching pattern on the adjacent traces. To determine the worst-case impedance swing due to crosstalk, it is necessary to pick the line in the bus that will experience the most crosstalk. A line in the center of the bus is usually the best choice. As mentioned earlier in the chapter, only the nearest-neighboring lines will contribute the majority of the crosstalk effects. Therefore, the procedures illustrated in previous examples can be used to calculate the impedance variation due to crosstalk. The patterns that produce the worst-case crosstalk effects will always be either common mode or differential mode. In

common mode the nets are all switching in phase, and in differential mode the target line is

always switching 180° out of phase with the other nets on the bus.

First, let's evaluate the effects of common-mode propagation (all bits switching in phase). Assume that line 2 in Figure 3.22 represents a conductor in the middle of the 8-bit bus.

Figure 3.22: Common-mode switching pattern.

Even-mode capacitance of conductors 2 and 1 = C22 - C12

Even-mode capacitance of conductors 2 and 3 = C22 - C23

Equivalent capacitance of conductor 2 = C22 - C12 - C23

Even-mode inductance of conductors 2 and 1 = L22 + L12

Even-mode inductance of conductors 2 and 3 = L22 + L23

Equivalent inductance of conductor 2 = L22 + L12 + L23

Therefore,

Now, let's evaluate the effects of differential-mode propagation. Assume that line 2 in Figure 3.23 represents a conductor in the middle of the 8-bit bus.

Figure 3.23: Differential switching pattern.

Odd-mode capacitance of conductors 2 and 1 = C22 + C12

Odd-mode capacitance of conductors 2 and 3 = C22 + C23

Equivalent capacitance of conductor 2 = C22 + C12 + C23

Even-mode inductance of conductors 2 and 1 = L22 - L12

Even-mode inductance of conductors 2 and 3 = L22 - L23

Equivalent inductance of conductor 2 = L22 - L12 - L23

Therefore,

The velocity and impedance variations due to crosstalk are as follows: 44.8 Ω < Z0 < 55.26 Ω

135 ps/in. < TD < 148.6 ps/in.

3.10.4. Determining if Crosstalk Will Induce False Triggers

A false trigger will occur if the signal has severe signal integrity problems. A receiver will trigger at its threshold. Typical CMOS buffers have a threshold voltage at Vcc. If the signal

rings back below the threshold level at the receiver, the signal integrity may cause a false trigger. If this happens in a digital system, it could cause a wide variety of problems, ranging from glitches in the data to catastrophic system failure (especially if the false trigger is on a strobe or clock signal).

To determine if the crosstalk will cause a false signal, it is necessary to evaluate the signal integrity. There are several methods of doing this. The simplest method is to use a simple bounce (i.e., lattice) diagram, such as was used to determine the wave shape of the signal in the Chapter 2 example. The full bounce diagram, however, is not required. Since the second reflection seen at the receiver will produce the highest magnitude of ringing, all that is required is the voltage level cause by the second reflection as seen at the receiver. Furthermore, the most ringing will occur when the driver impedance is low and the

transmission line impedance is high (see Chapter 2). Therefore, the worst-case ringing will be achieved when the coupled lines in the bus are propagating in phase with each other (i.e.,

common mode). The common-mode impedance was calculated above to be 55.2 Ω. The signal integrity is calculated using a bounce diagram as shown in Figure 3.24.

Figure 3.24: Calculation of the final waveform.

The signal will ring down to a minimum voltage of 1.84 V. Since the threshold voltage of this buffer was defined to be 1.0 V, and the signal does not ring back down below this value, the signal integrity will not cause a false triggering of the receiver.