Research Hypotheses

In this operation, the auxiliary switch S_L works as a chopper, but the main switches of the inverter do not turn on or off within a single PWM cycle when the phase current need not commutate. The load current is commu-tated when the DC link voltage becomes zero, that is, when the PWM signal is 0 (as the PWM cycle is very short, it does not affect the operation of the motor). The control scheme for the auxiliary switches in PWM operation is illustrated in Figure 7.6b.

• When the PWM signal is flipped from 1 to 0, mode 1 begins, the pulse signal for thyristor S_a is generated, and the gate signal for IGBT S_L drops to a low level. But the voltage of the DC link does not increase until the PWM signal is flipped from 0 to 1. Pulse CK is generated during mode 2.

• When the PWM signal is flipped from 0 to 1, mode 3 begins, and the pulse signal for thyristor S_b is generated (mode 3). Then when the voltage of the DC link is increased to E (voltage of supply), the gate signal for IGBT S_L is flipped to a high level (modes 4 and 5).

Thus, only one ZVT occurs per PWM cycle: modes 1 and 2 for PWM turned off, modes 3, 4, and 5 for PWM turned on. And the switching frequency would not be greater than the PWM frequency.

Normally, a drive system requires a speed or position feedback signal to get high speed or position precision and be less susceptible to disturbance of load and power supply. A speed feedback signal can be derived from a tachometer-generator, optical encoder, or resolver, or it can be derived from the rotor position sensor. The quadrature encoder pulse (QEP) is a standard digital speed or position signal and can be input to many devices (e.g., special DSP for drive system TMS320C24x has a QEP receive circuit). The QEP can be derived from the rotor position sensor of a BDCM easily. The converter digi-tal circuit and interesting waveforms are shown in Figure 7.7. Some single-chip computers have a digital counter and may require only direction and pulse signals; thus, the converter circuit can be simplified. The circuit can be implemented with a complex programmer logical device and only occupies part of one chip. The circuit can also be implemented by a gate array logic IC (e.g., 16V8) and a D flip-flop IC (e.g., 74LS74). With the circuit, a high-precision

Q

From rotor position sensor

A

Forward Direction change Reverse

(b) FIGURE 7.7

Circuit of derived QEP from Hall signal and waveforms.

speed or position signal can be obtained when the motor speed is high or the drive system has a high ratio speed reduction mechanism. In high-perfor-mance systems, the rotor position sensor may be a resolver or optical encoder, with special-purpose decoding circuitry. At this level of control sophistica-tion, it is possible to fine-tune the firing angles and the PWM control as a function of speed and load, to improve various aspects of performance such as efficiency, dynamic performance, or speed range.

7.1.4 Simulation and Experimental Results

The proposed topology is verified by Psim simulation software. The sche-matic circuit of the soft-switching inverter is shown in Figure 7.8. The left bottom of the figure is the auxiliary switches’ gate signal generator circuit (see Figure 7.6), which is made up of a monostable flip-flop, delay, and logical gate. The gate signals of auxiliary switches S_a and S_b in PWM and no-PWM operation modes are combined by an OR gate. The gate signal of S_L in the two operation modes is combined by an AND gate, and the synchronous signal (CK) is combined by a date selector. The middle bottom of the dia-gram shows the commutation logical circuit of the BDCM (see Figure 7.5); it is synchronized (by CK) with the auxiliary switches’ control circuit.

Waveforms of DC link voltage u_Cr, resonant inductor current i_Lr, BDCM phase current, inverter output line-line voltage, and gate signal of the auxil-iary switches are shown in Figure 7.9. The resonant inductor L_r has an induc-tance of 10 μH, and the resonant capacitor Cr has a capacitance of 0.047 μF, so the period of the resonant circuit is about 4 μs. The frequency of the PWM is 20 kHz. From the figure, we can see that the output of the simulation matches the theoretical analysis. The waveforms in Figure 7.9b, d, e, f, g, and h are the same as in Figure 7.10.

In order to verify the theoretical analysis and simulation results, the pro-posed soft-switching inverter was tested on an experimental prototype rated as follows:

DC link voltage 240 V Power of BDCM 3.3 Hp Switching frequency 10 kHz

A polyester capacitor of 47 nF, 1500 V, was adopted as the DC link resonant capacitor C_r. The resonant inductor had an inductance of 6 μH/20 A, with a ferrite core. The design of the auxiliary switches’ control circuit was refer-enced from Figure 7.8. The monostable flip-flop can be implemented with IC 74LS123, the delay can be implemented by a Schmitt trigger and an RC cir-cuit, and the logical gate can be replaced by a programmable logical device to reduce the number of ICs.

V VSL/DL E/2 Lr

ABDCM Speed sensor V V

Rotor position sensor Comm Commutate detector

A A

Ucr FIGURE 7.8 Schematic circuit of the drive system for Psim simulation.

10.00 (a) Current of phase a (b) Resonant capacitor voltage ucr

18085.00 (a) Voltage of phase a (b) Resonant inductor current (i_Lr)

18085.00

0.0018070.00 18075.00 18080.00 Time (us)

(e) Current of S_L (f) Sa gate signal

18085.00 18070.00 18075.00 18080.00 18085.00

Vgsa

0.0018070.00 18075.00 18080.00 Time (us)

(g) S_L gate signal (g) S_b gate signal

18085.00 18070.00 18075.00 18080.00 Time (us)

The waveforms of voltage across the switch and current under hard switching and soft switching are shown in Figures 7.10a and 7.10b, respec-tively. All the voltage signals come from differential probes, and there is a gain of 20. For voltage waveforms, 5.00 V/div = 100 V/div, which is the same for Figure 7.11. It can also be seen that there is a considerable overlap between the voltage and current waveforms under hard switching. The overlap is much less with soft switching.

The key waveforms with soft switching inverter are shown in Figure 7.11.

The default scale is as follows: DC link voltage: 100 V/div, current: 20 A/div. The default switching frequency is 10 kHz. The DC link voltage is

(a) Waveform of switch voltage and current

With hard switching (10 A/div) (b) Waveform of switch voltage and current With soft switching (10 A/div)

5.00 V

1 2 1.00 V 0.00 s 5.00 s 1

1

2

1

2 STOP 15.00 V2 1.00 V –400 n/s 5.00 µ/s 2 STOP

FIGURE 7.10

Voltage and current waveforms of switch SL in hard-switching and soft-switching inverters.

(a) Waveform of u_cr and S_a gate signal (b) Waveform of u_cr and S_b gate signal

(c) Waveform of u_cr and i_Lr (d) Waveform of phase voltage (L – L)

1

1 1

2

2 1

2 5.00 V

1 2 2.00 V 0.00 s 5.00 µ/s 1 STOP 15.00 V2 2.00 V 0.00 s 5.00 µ/s 1 STOP

5.00 V

1 2 2.00 V 0.00 s 5.00 µ/s 1 STOP 15.00 V 0.00 s 5.00 m/s 1STOP

FIGURE 7.11

Experiment waveforms.

fixed at 240 V. These experimental waveforms are similar to the simulation waveforms in Figure 7.9.