La Resolución 026 del 2006 del MAC aplicada a Unidades productoras.

The Miller plateau is a feature in the gate transient characteristics of power MOSFETs and IGBTs. Since the MOS gate terminals of power MOSFETs and IGBTs contain inherent parasitic capacitances that must be charged during turn-on and discharged during turn-off, the Miller plateau arises from the charging of these capacitors. Specifically, there are two parasitic capacitances related to the MOS gate namely, the gate-source capacitance and the gate-drain capacitance, otherwise known as the Miller capacitance. The gate-source (gate-emitter for IGBTs) capacitance arises from the overlap between the gate terminal and the n-doped source terminal whereas the gate-drain (gate-collector for IGBTs) capacitance arises from the over-lap between the gate and n- drift region. Both capacitances are dependent on the oxide thickness and overlap area. However, the gate-drain capacitance is a series combination of the oxide capacitance and the depletion capacitance arising from the space charge layer that is formed when the drift layer is blocking the DC voltage. Because the Miller capacitance is formed by the oxide capacitance as well as a voltage dependent depletion capacitance, it is a non-linear capacitances that decreases as the drain (collector for IGBT) voltage increases. This is due to the fact that the depletion width increases with the drain (collector for IGBT) voltage. Figure 2.23 shows the cross-section of a power MOSFET and the electrical schematic circuit diagram showing the parasitic capacitances (CGS, CGD and CDS),

parasitic body diode and main parasitic resistive elements (channel resistanceRCHand n-

2.3An overview of temperature sensitive electrical parameters for power devices

Figure 2.23 (a) Cross-section of a MOSFET (b) Electrical schematic of a MOSFET showing the parasitic capacitances (Adapted from [31])

Figure 2.24 shows a sketch of the gate-source voltage, drain-source current and drain-source voltage transients of a MOSFET (or an IGBT). As the gate voltage is increased between time t0 and t1, the gate-source capacitance is charged at a rate that

depends on the gate resistance and the gate-source (emitter for IGBT) capacitance. At time t1, when the threshold voltage is reached, the MOSFET (IGBT) channel conducts

current which rises until the load current value att2. At this point, the gate-source (emitter)

capacitor stops charging as the gate current is diverted to the gate-drain (collector) capacitance. The charging of the Miller capacitance precipitates the fall of the drain (collector) voltage from the off-state blocking value to the on-state value. For the duration of the t. At the point when the voltage transient ends, the Miller capacitance stops charging and the gate current is re-directed to the gate-source capacitance. This occurs at timet3in Figure 2.24.

2.3An overview of temperature sensitive electrical parameters for power devices

Figure 2.24 Idealised waveforms during the turn-on and turn-off transients of a MOSFET (Adapted from [21])

During the turn-off transient, the process occurs in the reverse direction, as it is observed in Figure 2.24. The gate voltage decreases exponentially until it reaches the plateau voltage VGPatt4. During the plateau time, the load current and the gate voltage

remain constant. The gate-drain (gate-collector) capacitance is discharged and the drain (emitter) voltage starts to increase. Once the plateau finishes and the drain voltage has reached the off-state value, at the instantt5,the gate capacitance continues to discharge

and the load current decreases until the threshold voltage is reached att6. Once the current

is zero, the gate voltage continues to decrease exponentially until it is zero. In the case of the IGBT, the transients are similar but there is a characteristic tail current caused by recombination of the charge carriers remaining in the device [31]).

The Miller plateau voltageVGPis shown in Figure 2.24 and is defined as the gate

voltage plateau level during the drain (collector) transient when the Miller capacitance is charged during turn-on and discharged during turn-off.

The temperature dependency of the Miller plateau is due to the drain (collector) voltage transient temperature dependency. The time duration of the plateau voltage has been identified as a TSEP in silicon IGBTs in [42]. Figure 2.25 shows measurements of IGBT gate transients at different temperatures where the temperature sensitivity of the

2.3An overview of temperature sensitive electrical parameters for power devices Miller plateau can be observed, while Figure 2.26 shows the impact of temperature on the turn-off transient of the collector-emitter voltage, which was evaluated as TSEP in [43].

Figure 2.25 Gate-Emitter voltage during turn-off of a Si IGBT at different temperatures

Figure 2.26 Collector-Emitter voltage during turn-off of a Si IGBT at different temperatures

Slowing down the device, by means of increasing the gate resistance increases the temperature sensitivity, as it can be observed in Figure 2.27.

2.3An overview of temperature sensitive electrical parameters for power devices

Figure 2.27 Impact of slowing down the turn-off of a Si IGBT on the gate-emitter voltage transient

In the case of silicon MOSFETs and IGBTs the delay between the instant when the gate is triggered and the instant when the current starts falling to zero can also be used as a TSEP. It has been evaluated for silicon IGBTs in [44], where the voltage across the parasitic emitter inductance was used as sensor. In the case of the IGBT, the impact of temperature is also observed in the tail current, as the results in Figure 2.28 show.

Figure 2.28 Collector-Emitter current during turn-off of a Si IGBT at different temperatures