Results and Discussion

The design of the PICDiY has been developed from scratch by utilizing VHDL language and basing on PIC16’s functionality, its architecture’s block diagram and its instruction set. Figure 4.1, obtained from the 16F84A data sheet, shows the block diagram of the PIC16. In order to obtain the simplest design, non essential elements of PIC16’s architecture have been discarded. The dismissed components are the timers (Power-up, oscillator Start-up, Watchdog and TMR0) and certain ports (only two ports are included). In addition, several adaptations have been introduced in order to optimize the architecture’s characteristics and functionality. Thanks to all these modifications, the design developed in this work is a small processor with flexible functionality and complete self-sufficiency. The main features of the architecture, the different components and the adaptations made are discussed in detail through this section.

As shown in Figure 4.2, the PICDiY consist of different blocks: the Arithmetic Logic Unit (ALU), the program counter, the Instruction Decoder and Controller (IDC), the 8-level stack, program and data memory blocks, address and data multiplexers and the different special function registers. Due to its Harvard ar-chitecture, separate storage and buses for instructions and data are implemented,

FLASH

Figure 4.1: Block diagram of the PIC16.

allowing faster access and different bus width for instruction and data. The widths are 14 bits for the program memory and 8 bits for the data memory. The data bus includes a multiplexer structure, not shown in the figure to facilitate the comprehension. Control signals, such as, enables, mux controls, etc. (which mainly are generated by the IDC) are also omitted for the same reason. The processor also has an 8-bit PORTA, clock, reset and interrupt inputs (both clock and reset inputs are also not shown in the figure) and an 8-bit PORTB output directly connected to the PORTB register. In this way, PORTA and PORTB are physical connections between the processor and external peripherals for data transmission. Only two ports are implemented for achieving a minimal usage of FPGA resources, nevertheless, the number of ports can be easily changed by modifying the VHDL files of the design.

The special function registers are an area of data memory dedicated to registers that are required for configuration and control, which can not be used as general purpose registers by the user. Since each of the special function register has a spe-cific functionality, in the case of the PICDiY, each of them have been implemented on separated blocks outside the data memory block. In this way, the PICDiY con-tains seven register-blocks (FSR, STATUS, PCL, PCLATH, INTCON, PORTB and W) of eight bit width. The registers related to the discarded components

Interruption

Figure 4.2: Block diagram of the PICDiY.

(TMR, EEDATA, EEADR, OPTION, TRISA, TRISB, EECON1 and EECON2) have not been implemented in the PICDiY due to obvious reasons.

The STATUS register is one of the most relevant registers when programming the processor, since it contains the arithmetic status of the ALU, the RESET status and the bank select bit for the data memory. As all the special function registers, the STATUS register can be the destination for any instruction. Figure 4.3 shows the different bits of the STATUS register. The first three bits are the carry (C), digit carry (DC) and zero (Z) flags of the ALU, respectively and their values vary depending on the results of logical or arithmetic operations. Bits three and four (power down and watchdog timer timeout) are unused since they are related to functions not implemented in the PICDiY. Finally, bit five (RP0) and bit six (RP1) are the bank selection bits. Bearing in mind that PICDiY’s data memory has only two banks, RP1 is not used. However, it could be used in future adaptations if a larger data memory is required.

IRP RP1 RP0 TO PD Z DC C

The FSR (File Select Register) is used for indirect addressing to other file regis-ters. If a file register address is loaded into the FSR register, the content of that file register can be indirectly read or written. This register is usually used as a pointer to a block of locations. Reading the FSR itself indirectly results in a 00h, while writing to itself indirectly results in a no-operation (STATUS bits could be altered).

The PCL register (Program Counter Low Byte) and the PCLATH (Program Counter Latch High) registers are used to store instruction’s addresses to be loaded in the program counter. Both registers, which are fully readable and writable, are required because the length of the program counter can be up to 13 bits (depending of the depth of the Program Memory). Figure 4.4 depicts how the bits are distributed when data is load to the program counter and, as it can be observed, several bits of the PCLATH register are unused. Since the depth of the program memory can be modified, the quantity of the unused bits may vary.

For instance, in the case of a program memory of 256 instructions depth the eight bits of the PCL are sufficient, leaving all the five bits of the PCLATH unused.

The adaptation of these characteristics require minor changes in the HDL design.

bit0

Figure 4.4: PCL and PCLATH registers.

The INTCON is a readable and writable register utilized to control the interrup-tions. Since a single type of interruption is implemented for the PICDiY, only the seventh bit is used to store the interruption state. The management of this bit is performed by the IDC.

The W register (Working register) is used for ALU operations as an operand.

It is not an addressable register. Nevertheless, it can be read and written by using some instructions, because it also can be used to store the results of oper-ations. For instance, MOVWF and MOVF instructions can move the values from the W register to any location in the data memory, and vice-versa.

The ALU (Arithmetic Logic Unit) is an 8-bit block responsible for performing arithmetic operations such as adding, subtracting, decreasing and increasing, logic operations such as AND, OR, XOR and IOR and other operations like

Figure 4.5: State diagram of IDC’s FSM.

shifting (right or left within a register), swapping or not operation. Depending on the 8th bit of the instruction word, the result is sent to the W register (when

’0’) or to another register (when ’1’) like RAM Data memory, FSR or PORTB.

According to which instruction is executed, the ALU can affect values of zero, carry or digit carry bits of the STATUS register.

The IDC is responsible of managing the processor’s resources. After decoding each instruction, it controls different elements of the processor, such as, the ALU, the multiplexers, the different registers, the DATA memory and even the program counter. It is implemented as four states Finite States Machine (FSM). This is the reason why the execution of each instruction takes four clock cycles. Figure 4.5 presents the IDS’s FSM and as it can be observed, in the first state the IDC activates the instruction reading from the program memory. The second state depending of the instruction, is used to read data or to load the correct next instruction on the program counter, when CALL, GOTO or RETURN instructions are executed. In the third state, if necessary, the IDC enables the writing in the data memory. Finally, the last state is used for data stabilization and for the interruption management.

In PIC16’s architecture the data memory is divided into two areas. The first area is composed by the special function registers, while the second is the user-data memory. Since, the PICDiY’s special function registers are implemented in sep-arate blocks, its data memory block includes only the user-data memory, which has been implemented utilizing the dedicated BRAMs [327] in order to optimize the utilization of resources when using Xilinx FPGAs. In this way, the synthe-sizer will use the Xilinx FPGAs dedicated BRAM resources, avoiding the use of distributed RAM that would use more logic cells. Nevertheless, memories can be easily implemented in other vendors’ devices by using their specific resources,

thus, maintaining platform independence. The data memory is banked in two blocks to permit a larger memory storage and each bank extends up to 7Fh (128 bytes). As it has been commented before, the bank selection is done by writing the STATUS register’s RP0 bit. In this way, Bank 0 is selected by clearing the RP0 bit of the STATUS register and the selection of Bank 1 is done by setting this bit to one. All the data memory addresses can be accessed either directly by utilizing the absolute address of each register or indirectly. When indirect option is selected, using the zero address in the data memory, the processor uses the FSR register to store the data in the correct address. Indirect addressing also utilizes the value of the RP0 bit to access the banked areas of data memory.

Figure 4.6 shows the mapping of the memories. As it can be seen, the first twelve locations of each bank are reserved for the special function registers and the re-maining locations are used for the user-data memory. The reason to reserve those initial addresses unused is to maintain coherence with PIC16’s architecture and its instruction set. In this way, despite the fact that the special function registers are implemented outside the data memory module, they can be accessed using their original addresses thanks to the IDC, which controls the enable port of each register.

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Figure 4.6: Mapping of PICDiY’s user-data memory and registers.

The program memory block is responsible to store the instructions to be executed by the processor. Similarly to the data memory block, it is implemented by using BRAMs. However, the data length is 14 bits. Another remarkable difference is that it is implemented as a read only memory. Thus, the instructions must be written in the HDL file. In favour of easing the programming task, the HEX2VHD for PICDiY software has been developed in this work. This software generates a VHDL file of the program memory from a HEX file. This HEX file can be obtained in a straightforward fashion by using a PIC16-compatible IDE, like the MPLAB by Microchip Technology Inc.

The program counter block manages the execution sequence of program memory’s instructions, loading the next instruction or jumping to another one when CALL, GOTO, RETURN, indirect instructions or an interrupt are executed. It is a 13 bit block capable of addressing an 8K x 14 memory space.