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The SiC JFET was fabricated in early stage to realize the performance of SiC devices. There was so many drawbacks with these devices in early stage like low transconductance (i.e. the slope of the transfer characteristics in the active region) values, low channel mobilities and difficulties in the fabrication process. Later on the improvement on the SiC material and fabricated with the advance technology and first prototype samples of SiC JFETs were released in the market.

The modern designs of SiC JFET, which is named as lateral channel JFET (LCJFET) is shown in Fig. 3.8 [6]. The SiC JFET is a normally on device and to make it turn off require to feed a negative gate to source voltage. By applying a negative gate-source voltage, a certain space charge region develops, and hence width of channel is decreased and reduction in current is obtained. The specific value of gate-source voltage is called pinch-off voltage and under this voltage, the device current equals zero. The normal range of pinch-off voltages of this device is between -16 V and -26 V. The SiCED (Infineon) already released these types of SiC devices few years ago and it will be commercial in near future.

The Semisouth Laboratories released second type of available commercial SiC JFET that is vertical trench (VTJFET) in 2008. The schematic diagram of SiC VTJFET is shown in Fig. 3.9. The SiC VTJFET can be work either in normally off i.e. enhancement mode vertical trench junction field effect transistor (EMVTJFET) or in normally on i.e. depletion mode

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vertical trench junction field effect transistor (DMVTJFET) devices. The working function of devices depends on the thickness of the vertical channel and the doping levels of the structure. For the normally on JFET, a negative gate-source voltage is required to make it turn off. Once devices turned off, very low current is required to keep the JFET in off state. The pinch-off voltage for the DMVTJFET equals approximately -6V, while the positive pinch-off voltage for the normally off devices (EMVTJFET) is slightly higher than 1V.

The other additional SiC JFET designs are shown in Figs. 3.10 and 3.11. There are two different types of design, which are more commercial in the market. The schematic diagram of the cross section of buried grid JFET (BGJFET) is shown in Fig. 3.10, in which small cell pitch has been used which contributes to the low specific on state resistance and high saturation current densities. Moreover, the inherent similarities in the gate drive and the wide design window for the channel length, width, and level of doping make these devices more suitable for the power converters. The basic two disadvantages in designing this device as

Fig. 3.9 Cross section of the SiC VTJFET

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compared to LCJFET, first is that they are more difficult to fabricate and other one is the absence of antiparallel body diode. In the case of implanted grid, the use of high doping in the channel is limited by the necessity to compensate the high-doped n-layer on top of the drift layer by the p-grid implant. The level of doping for the channel is limited by the tolerances of the photolithography and the trench etching process.

The double gate vertical channel trench JFET (DGVTJFET) is shown in Fig. 3.11, which is the combination of advantages of LCJFET and the BGJFET designs. The DGVTJFET offers the high current rating capabilities for normally off mode operation. Because of the small cell pitch and double gate control, this design is able to combine fast switching capability due to the low gate-drain capacitance with low specific on-state resistance. Normally off devices have high saturation current level because of the double gate driver and wide design window for the channel optimization. Moreover, due to the possibilities of using highly doped channels, the negative temperature dependence of the saturation current is reduced. Hence, these devices have advantages of the BGJFET, but the performance of BGJFET can surpass them due to the larger design window for the channel doping and width. Therefore, the gate to drain body p-n diode can be used in this process, but it is a matter of trade off with the possible saturation current density.

The SiC JFETs are commercially available of the rating of 1200V to 1700V. The normally on JFETs have the current rating up to 48A and on state resistances of 100, 85, 45 mΩ at the room temperature. Similarly, the normally off JFETs (EMVTJFETs) are available in market with the current rating up to 30A and on state resistances of 100 and 63 mΩ. Fig. 3.12 shows the on state voltage versus blocking voltage for various unipolar and bipolar SiC and Si power devices, in which there is a huge difference between the Si and SiC devices. Fig. 3.13 shows specific on-state resistance with the variation of temperature for different JFET structures. It can be observe that normally off devices have a weaker temperature dependence compared to the normally on devices [7]. The specific Ron of the normally off devices is dominated to a large extent by the channel resistance.

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Fig. 3.13 Temperature dependence of the specific on-state resistance for different JFET structures

Fig. 3.14 Comparison of the top gate (red line) and double gate (blue line) switching characteristics of the normally-on LCJFET structure with 16 μm cell pitch

Fig. 3.12 On-state voltage versus blocking voltage for various unipolar and bipolar SiC and Si power devices

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Fig. 3.14 shows the comparison of the top gate (red line) and double gate (blue line) switching characteristics of the normally on LCJFET structure with 16 μm cell pitch. The gate charge and turn-off losses have the high values in the top gate control as compared to double gate control, while the driving condition is the same for both cases. It can be observed from Fig. 3.14, the normally off LCJFET will necessarily suffer from slow switching speed since it needs double gate control in order to pass reasonable forward currents. The same comparison is shown in Fig. 3.15 for the normally off DGVTJFET structure and normally off LCJFET structure with cell pitch of 10 μm [7]. The overall turn off switching comparison shows that the sacrifice of the switching speed is much less severe for the DGVTJFET structure due to the much smaller cell pitch and thus the smaller Miller capacitance attributed to both the buried and top gates, respectively.