2. CAPÍTULO II: REVISIÓN DE LA LITERATURA E HIPÓTESIS DE PARTIDA
2.1. REVISIÓN DE LA LITERATURA
2.1.2. Teoría General y Variables
2.1.2.1. Signo
The first chapter presents a brief introduction of the future trends in emerging memory devices, especially memristor-based memories. Then, statement of the problem and thesis objectives are established. In addition, research questions and emerging thesis contributions are demonstrated.
© COPYRIGHT
UPM
12
Chapter 2 presents a comprehensive literature review of memristor models and sneak path current problem associated with memristive crossbar array memory. It begins with the exploration of the memristor and the development of different device models. Then, several applications of the memristor device are reported. Lastly, memristor crossbar arrays are explained focusing on the sneak path current problem. Previously proposed solutions are extensively reviewed and compared to identify the advantages and limitations of each solution.
Chapter 3 presents the research methodology in details. First of all, a SRM model is proposed while completely describing each development stage to achieve the first thesis objective. Later, it presents the development of modified crossbar structures and the integration of memristor device, achieving the second objective. Lastly, the complete read and write procedures are described and the system performance metrics to be collected and processed are also defined.
In chapter 4, the developed system is simulated and raw data are collected. After processing the acquired data, performance metrics are presented for memory read and write operations individually to achieve the third objective. In addition, performance benchmarking is accomplished in order to verify the improvement of the proposed system against other related studies.
In chapter 5, a conclusion of the thesis is introduced, followed by reporting the contributions of the this research. Lastly, few recommended future research directions are proposed for further inspection.
© COPYRIGHT
UPM
186
REFERENCES
[1] D. C. Brock and G. E. Moore, Understanding Moore's law: four decades of
innovation. Philadelphia, Pa : Chemical Heritage Press, 2006.
[2] R. R. Schaller, "Moore's law: past, present and future," IEEE spectrum, vol. 34, no. 6, pp. 52-59, 1997.
[3] D. R. Cumming, S. B. Furber, and D. J. Paul, "Beyond Moore's law,"
Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences, vol. 372, no. 2012, 2014.
[4] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proceedings of the IEEE, vol. 89, no. 3, pp. 259-288, 2001. [5] K. Likharev, "Electronics below 10 nm," Nano and Giga Challenges in
Microelectronics, pp. 27-68, 2003.
[6] S. Kim and C. H. Lam, "Transition of memory technologies," in VLSI
Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on, 2012, pp. 1-3.
[7] J. S. Meena, S. M. Sze, U. Chand, and T.-Y. Tseng, "Overview of emerging nonvolatile memory technologies," Nanoscale Research Letters, vol. 9, no. 1, p. 526, 2014.
[8] A. Chen, "A review of emerging non-volatile memory (NVM) technologies and applications," Solid-State Electronics, vol. 125, pp. 25-38, 2016.
[9] "International Technology Roadmap for Semiconductors (ITRS): Beyond
CMOS," 2015. [Online]. Available:
https://www.semiconductors.org/clientuploads/Research_Technology/ITRS/2 015/6_2015 ITRS 2.0 Beyond CMOS.pdf. Accessed on: June 3, 2017.
[10] L. Chua, "Memristor-the missing circuit element," IEEE Transactions on
circuit theory, vol. 18, no. 5, pp. 507-519, 1971.
[11] D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, "The missing memristor found," Nature, vol. 453, no. 7191, pp. 80-83, 2008.
[12] I. Vourkas, D. Stathis, and G. C. Sirakoulis, "Improved read voltage margins with alternative topologies for memristor-based crossbar memories," in VLSI-
SoC, 2013, pp. 336-339.
[13] G. C. Adam, B. D. Hoskins, M. Prezioso, F. Merrikh-Bayat, B. Chakrabarti, and D. B. Strukov, "3-D memristor crossbars for analog and neuromorphic computing applications," IEEE Transactions on Electron Devices, vol. 64, no. 1, pp. 312-318, 2017.
[14] S. Yu, Resistive Random Access Memory (RRAM): from devices to array
architectures. San Rafael, California : Morgan & Claypool Publishers, 2016.
[15] D. B. Strukov and K. K. Likharev, "Prospects for terabit-scale nanoelectronic memories," Nanotechnology, vol. 16, no. 1, p. 137, 2004.
[16] Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "Sneak-path constraints in memristor crossbar arrays," in Information Theory Proceedings (ISIT), IEEE
International Symposium on, 2013, pp. 156-160.
[17] M. A. Zidan, H. A. H. Fahmy, M. M. Hussain, and K. N. Salama, "Memristor-based memory: The sneak paths problem and solutions,"
© COPYRIGHT
UPM
187
[18] Y. Gao, O. Kavehei, S. F. Al-Sarawi, D. C. Ranasinghe, and D. Abbott, "Read operation performance of large selectorless cross-point array with self- rectifying memristive device," INTEGRATION, the VLSI journal, vol. 54, pp. 56-64, 2016.
[19] L. Song, J. Zhang, A. Chen, H. Wu, H. Qian, and Z. Yu, "An efficient method for evaluating RRAM crossbar array performance," Solid-State
Electronics, vol. 120, pp. 32-40, 2016.
[20] C. Xu, D. Niu, Y. Zheng, S. Yu, and Y. Xie, "Impact of cell failure on reliable cross-point resistive memory design," ACM Transactions on Design
Automation of Electronic Systems (TODAES), vol. 20, no. 4, p. 63, 2015.
[21] I. Vourkas, D. Stathis, G. C. Sirakoulis, and S. Hamdioui, "Alternative architectures toward reliable memristive crossbar memories," IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 1,
pp. 206-217, 2016.
[22] L. O. Chua and S. M. Kang, "Memristive devices and systems," Proceedings
of the IEEE, vol. 64, no. 2, pp. 209-223, 1976.
[23] L. Chua, "Resistance switching memories are memristors," Applied Physics
A, vol. 102, no. 4, pp. 765-783, 2011.
[24] D. Biolek, Z. Biolek, V. Biolková, and Z. Kolka, "Some fingerprints of ideal memristors," in IEEE International Symposium on Circuits and Systems
(ISCAS2013), 2013, pp. 201-204.
[25] D. Biolek, Z. Biolek, and V. Biolkova, "Pinched hysteretic loops of ideal memristors, memcapacitors and meminductors must be'self-crossing',"
Electronics letters, vol. 47, no. 25, pp. 1385-1387, 2011.
[26] S. R. Ovshinsky, R. R. Johnson, V. D. Cannella, and Z. Yaniv, "Programmable semiconductor structures and methods for using the same," U.S. Patent 4 646 266 A, Feb. 24, 1987.
[27] S. Thakoor, A. Moopenn, T. Daud, and A. Thakoor, "Solid‐state thin‐film memistor for electronic neural networks," Journal of Applied Physics, vol. 67, no. 6, pp. 3132-3135, 1990.
[28] K. Nichogi, A. Taomoto, S. Asakawa, and K. Yoshida, "Artificial neural function circuit having organic thin film elements," U.S. Patent 5 223 750 A, Jun. 29, 1993.
[29] F. Buot and A. Rajagopal, "Binary information storage at zero bias in quantum‐well diodes," Journal of applied physics, vol. 76, no. 9, pp. 5552- 5560, 1994.
[30] A. Beck, J. Bednorz, C. Gerber, C. Rossel, and D. Widmer, "Reproducible switching effect in thin oxide films for memory applications," Applied
Physics Letters, vol. 77, no. 1, pp. 139-141, 2000.
[31] P. J. Kuekes, R. S. Williams, and J. R. Heath, "Molecular wire crossbar memory," U.S. Patent 6 128 214 A, Oct. 3, 2000.
[32] Y. Chen, G.-Y. Jung, D. A. Ohlberg, X. Li, D. R. Stewart, J. O. Jeppesen, et
al., "Nanoscale molecular-switch crossbar circuits," Nanotechnology, vol. 14,
no. 4, p. 462, 2003.
[33] S. Liu, N. Wu, and A. Ignatiev, "A new concept for non-volatile memory: The electric-pulse induced resistive change effect in colossal magnetoresistive thin films," in Non-Volatile Memory Technology
© COPYRIGHT
UPM
188
[34] D. Stewart, D. Ohlberg, P. Beck, Y. Chen, R. S. Williams, J. O. Jeppesen, et
al., "Molecule-independent electrical switching in Pt/organic monolayer/Ti
devices," Nano Letters, vol. 4, no. 1, pp. 133-136, 2004.
[35] G. Snider, "Computing with hysteretic resistor crossbars," Applied Physics A, vol. 80, no. 6, pp. 1165-1172, 2005.
[36] R. Waser and M. Aono, "Nanoionics-based resistive switching memories,"
Nature materials, vol. 6, no. 11, pp. 833-840, 2007.
[37] G. S. Snider, "Self-organized computation with unreliable, memristive nanodevices," Nanotechnology, vol. 18, no. 36, p. 365202, 2007.
[38] R. S. Williams, "How we found the missing memristor," IEEE spectrum, vol. 45, no. 12, pp. 28-35, 2008.
[39] B. Hayes, "The memristor," American Scientist, vol. 99, no. 2, pp. 106-110, 2011.
[40] R. Waser, R. Dittmann, G. Staikov, and K. Szot, "Redox‐based resistive switching memories–nanoionic mechanisms, prospects, and challenges,"
Advanced materials, vol. 21, no. 25‐26, pp. 2632-2663, 2009.
[41] H.-S. P. Wong, H.-Y. Lee, S. Yu, Y.-S. Chen, Y. Wu, P.-S. Chen, et al., "Metal–oxide RRAM," Proceedings of the IEEE, vol. 100, no. 6, pp. 1951- 1970, 2012.
[42] K. Yan, M. Peng, X. Yu, X. Cai, S. Chen, H. Hu, et al., "High-performance perovskite memristor based on methyl ammonium lead halides," Journal of
Materials Chemistry C, vol. 4, no. 7, pp. 1375-1381, 2016.
[43] D. E. Root, "Future device modeling trends," IEEE Microwave Magazine, vol. 13, no. 7, pp. 45-59, 2012.
[44] P. Meuffels and R. Soni, "Fundamental issues and problems in the realization of memristors," arXiv:1207.7319, Jul. 2012.
[45] D. B. Strukov, J. L. Borghetti, and R. S. Williams, "Coupled ionic and electronic transport model of thin‐film semiconductor memristive behavior,"
Small, vol. 5, no. 9, pp. 1058-1063, 2009.
[46] Y. V. Pershin and M. Di Ventra, "Memory effects in complex materials and nanoscale systems," Advances in Physics, vol. 60, no. 2, pp. 145-227, 2011. [47] J. J. Yang, M. D. Pickett, X. Li, D. A. Ohlberg, D. R. Stewart, and R. S.
Williams, "Memristive switching mechanism for metal/oxide/metal nanodevices," Nature nanotechnology, vol. 3, no. 7, pp. 429-433, 2008. [48] M. D. Pickett, D. B. Strukov, J. L. Borghetti, J. J. Yang, G. S. Snider, D. R.
Stewart, et al., "Switching dynamics in titanium dioxide memristive devices,"
Journal of Applied Physics, vol. 106, no. 7, p. 074508, 2009.
[49] N. R. McDonald, R. E. Pino, P. J. Rozwood, and B. T. Wysocki, "Analysis of dynamic linear and non-linear memristor device models for emerging neuromorphic computing hardware design," in The International Joint
Conference on Neural Networks (IJCNN), 2010, pp. 1-5.
[50] A. G. Radwan and M. E. Fouda, On the mathematical modeling of
memristor, memcapacitor, and meminductor. Springer International, 2015.
[51] T. Wey and S. Benderli, "Amplitude modulator circuit featuring TiO2
memristor with linear dopant drift," Electronics letters, vol. 45, no. 22, pp. 1103-1104, 2009.
© COPYRIGHT
UPM
189
[52] V. Keshmiri, "A study of the memristor models and applications," M.S thesis, Department of Electrical Engineering, Linköping universitet, Linköping, Sweden, 2014.
[53] Y. N. Joglekar and S. J. Wolf, "The elusive memristor: properties of basic electrical circuits," European Journal of Physics, vol. 30, no. 4, p. 661, 2009. [54] D. Biolek, V. Biolkova, and Z. Biolek, "SPICE model of memristor with
nonlinear dopant drift," Radioengineering, vol. 18, no. 2, pp. 210-214, 2009. [55] T. Prodromakis, B. P. Peh, C. Papavassiliou, and C. Toumazou, "A versatile
memristor model with nonlinear dopant kinetics," IEEE transactions on
electron devices, vol. 58, no. 9, pp. 3099-3105, 2011.
[56] J. Yu, X. Mu, X. Xi, and S. Wang, "A memristor model with piecewise window function," Radioengineering, vol. 22, no. 4, pp. 969-974, 2013. [57] S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "TEAM:
threshold adaptive memristor model," IEEE Transactions on Circuits and
Systems I: Regular Papers, vol. 60, no. 1, pp. 211-221, 2013.
[58] Y. Takahashi, T. Sekine, and M. Yokoyama, "SPICE model of memristive device using Tukey window function," IEICE Electronics Express, no. 0, 2015.
[59] J. Chowdhury, J. Das, and N. Rout, "Trigonometric window functions for memristive device modeling," in Fifth International Conference on Advanced
Computing & Communication Technologies, 2015, pp. 157-161.
[60] D. B. Strukov and R. S. Williams, "Exponential ionic drift: fast switching and low volatility ofáthin-film memristors," Applied Physics A, vol. 94, no. 3, pp. 515-519, 2009.
[61] E. Lehtonen and M. Laiho, "CNN using memristors for neighborhood connections," in Proc. Int. Workshop Cell. Nanoscale Netw. Their Appl, 2010, pp. 1-4.
[62] C. Yakopcic, T. M. Taha, G. Subramanyam, R. E. Pino, and S. Rogers, "A memristor device model," IEEE electron device letters, vol. 32, no. 10, pp. 1436-1438, 2011.
[63] S. Kvatinsky, M. Ramadan, E. G. Friedman, and A. Kolodny, "VTEAM: a general model for voltage-controlled memristors," IEEE Transactions on
Circuits and Systems II: Express Briefs, vol. 62, no. 8, pp. 786-790, 2015.
[64] S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and W. Lu, "Nanoscale memristor device as synapse in neuromorphic systems," Nano
letters, vol. 10, no. 4, pp. 1297-1301, 2010.
[65] A. S. Oblea, A. Timilsina, D. Moore, and K. A. Campbell, "Silver chalcogenide based memristor devices," in Neural Networks (IJCNN), The
International Joint Conference on, 2010, pp. 1-3.
[66] X. Wang, Y. Chen, H. Xi, H. Li, and D. Dimitrov, "Spintronic memristor through spin-torque-induced magnetization motion," IEEE electron device
letters, vol. 30, no. 3, pp. 294-297, 2009.
[67] H.-S. P. Wong, S. Raoux, S. Kim, J. Liang, J. P. Reifenberg, B. Rajendran, et
al., "Phase change memory," Proceedings of the IEEE, vol. 98, no. 12, pp.
2201-2227, 2010.
[68] B. Xu, Y. Shen, X. Wang, and L. Chen, "Efficient memristor model implementation for simulation and application," IEEE Transactions on
© COPYRIGHT
UPM
190
Computer-Aided Design of Integrated Circuits and Systems, pp. 1226-1230,
2017.
[69] E. Linn, R. Rosezin, C. Kügeler, and R. Waser, "Complementary resistive switches for passive nanocrossbar memories," Nature materials, vol. 9, no. 5, pp. 403-406, 2010.
[70] K.-H. Kim, S. Gaba, D. Wheeler, J. M. Cruz-Albrecht, T. Hussain, N. Srinivasa, et al., "A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications," Nano letters, vol. 12, no. 1, pp. 389-395, 2011.
[71] Y. Gao, D. C. Ranasinghe, S. F. Al-Sarawi, O. Kavehei, and D. Abbott, "mrPUF: A novel memristive device based physical unclonable function," in
International Conference on Applied Cryptography and Network Security,
2015, pp. 595-615.
[72] E. Gale, "TiO2-based memristors and ReRAM: materials, mechanisms and
models (a review)," Semiconductor Science and Technology, vol. 29, no. 10, p. 104004, 2014.
[73] S. N. Truong and K.-S. Min, "New memristor-based crossbar array architecture with 50-% area reduction and 48-% power saving for matrix- vector multiplication of analog neuromorphic computing," Journal of
semiconductor technology and science, vol. 14, no. 3, pp. 356-363, 2014.
[74] X. Shi, S. Duan, L. Wang, T. Huang, and C. Li, "A novel memristive electronic synapse-based Hermite chaotic neural network with application in cryptography," Neurocomputing, vol. 166, pp. 487-495, 2015.
[75] J. J. Yang, D. B. Strukov, and D. R. Stewart, "Memristive devices for computing," Nature nanotechnology, vol. 8, no. 1, pp. 13-24, 2013.
[76] F. Corinto, A. Ascoli, and M. Gilli, "Nonlinear dynamics of memristor oscillators," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 6, pp. 1323-1336, 2011.
[77] M. Itoh and L. O. Chua, "Memristor oscillators," International Journal of
Bifurcation and Chaos, vol. 18, no. 11, pp. 3183-3206, 2008.
[78] A. Talukdar, A. G. Radwan, and K. N. Salama, "Non linear dynamics of memristor based 3rd order oscillatory system," Microelectronics journal, vol. 43, no. 3, pp. 169-175, 2012.
[79] A. Talukdar, A. G. Radwan, and K. N. Salama, "Generalized model for memristor-based Wien family oscillators," Microelectronics Journal, vol. 42, no. 9, pp. 1032-1038, 2011.
[80] M. A. Zidan, H. Omran, C. Smith, A. Syed, A. G. Radwan, and K. N. Salama, "A family of memristor‐based reactance‐less oscillators,"
International Journal of Circuit Theory and Applications, vol. 42, no. 11, pp.
1103-1122, 2014.
[81] B. Muthuswamy, "Implementing memristor based chaotic circuits,"
International Journal of Bifurcation and Chaos, vol. 20, no. 05, pp. 1335-
1350, 2010.
[82] B. Bo-Cheng, H. Wen, X. Jian-Ping, L. Zhong, and Z. Ling, "Analysis and implementation of memristor chaotic circuit," Acta Physica Sinica, vol. 60, no. 12, p. 120502, 2011.
© COPYRIGHT
UPM
191
[83] A. Buscarino, L. Fortuna, M. Frasca, and L. V. Gambuzza, "A chaotic circuit based on Hewlett-Packard memristor," Chaos: An Interdisciplinary Journal
of Nonlinear Science, vol. 22, no. 2, p. 023136, 2012.
[84] S. Shin, K. Kim, and S.-M. Kang, "Memristor-based fine resolution programmable resistance and its applications," in Communications, Circuits
and Systems, 2009. ICCCAS 2009. International Conference on, 2009, pp.
948-951.
[85] S. Shin, K. Kim, and S.-M. Kang, "Memristor applications for programmable analog ICs," IEEE Transactions on Nanotechnology, vol. 10, no. 2, pp. 266- 274, 2011.
[86] T. Wey and W. Jemison, "An automatic gain control circuit with TiO2
memristor variable gain amplifier," Analog Integrated Circuits and Signal
Processing, vol. 73, no. 3, pp. 663-672, 2012.
[87] R. Berdan, T. Prodromakis, I. Salaoru, A. Khiat, and C. Toumazou, "Memristive devices as parameter setting elements in programmable gain amplifiers," Applied Physics Letters, vol. 101, no. 24, p. 243502, 2012. [88] T. Ibrayev, I. Fedorova, A. K. Maan, and A. P. James, "On design of
memristive amplifier circuits," Circuits and Systems, vol. 5, no. 11, p. 265, 2014.
[89] A. Ascoli, R. Tetzlaff, F. Corinto, M. Mirchev, and M. Gilli, "Memristor- based filtering applications," in 14th Latin American Test Workshop-LATW, 2013, pp. 1-6.
[90] W. Wang, Q. Yu, C. Xu, and Y. Cui, "Study of filter characteristics based on PWL memristor," in Communications, Circuits and Systems, ICCCAS 2009.
International Conference on, 2009, pp. 969-973.
[91] Ş. Yener, R. Mutlu, and H. H. Kuntman, "Analysis of filter characteristics based on PWL memristor," IU-Journal of Electrical & Electronics
Engineering, vol. 14, no. 1, pp. 1709-1719, 2014.
[92] E. Linn, R. Rosezin, S. Tappertzhofen, and R. Waser, "Beyond von Neumann? logic operations in passive crossbar arrays alongside memory operations," Nanotechnology, vol. 23, no. 30, p. 305205, 2012.
[93] E. Lehtonen and M. Laiho, "Stateful implication logic with memristors," in
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009, pp. 33-36.
[94] S. Kvatinsky, G. Satat, N. Wald, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristor-based material implication (IMPLY) logic: design principles and methodologies," IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, vol. 22, no. 10, pp. 2054-2066, 2014.
[95] J. Borghetti, G. S. Snider, P. J. Kuekes, J. J. Yang, D. R. Stewart, and R. S. Williams, "‘Memristive’switches enable ‘stateful’logic operations via material implication," Nature, vol. 464, no. 7290, pp. 873-876, 2010.
[96] A. Raghuvanshi and M. Perkowski, "Logic synthesis and a generalized notation for memristor-realized material implication gates," in Proceedings
of the 2014 IEEE/ACM International Conference on Computer-Aided Design, 2014, pp. 470-477.
[97] E. Lehtonen, J. Poikonen, and M. Laiho, "Two memristors suffice to compute all Boolean functions," Electronics letters, vol. 46, no. 3, p. 230, 2010.
© COPYRIGHT
UPM
192
[98] E. Lehtonen, J. H. Poikonen, and M. Laiho, "Applications and limitations of memristive implication logic," in 13th International Workshop on Cellular
Nanoscale Networks and their Applications, 2012, pp. 1-6.
[99] O. Kavehei, "Memristive devices and circuits for computing, memory, and neuromorphic applications," Ph.D. dissertation, School of Electrical and Electronic Engineering, The University of Adelaide, Australia, 2011.
[100] Y. Ho, G. M. Huang, and P. Li, "Nonvolatile memristor memory: device characteristics and design implications," in Proceedings of the 2009
International Conference on Computer-Aided Design, 2009, pp. 485-490.
[101] Y. Ho, G. M. Huang, and P. Li, "Dynamical properties and design analysis for nonvolatile memristor memories," IEEE Transactions on Circuits and
Systems I: Regular Papers, vol. 58, no. 4, pp. 724-736, 2011.
[102] R. I. Bahar, D. Hammerstrom, J. Harlow, W. H. Joyner, C. Lau, D. Marculescu, et al., "Architectures for silicon nanoelectronics and beyond,"
IEEE Computer, vol. 40, no. 1, pp. 25-33, 2007.
[103] H. Y. Jeong, Y. I. Kim, J. Y. Lee, and S.-Y. Choi, "A low-temperature-grown TiO2-based device for the flexible stacked RRAM application," Nanotechnology, vol. 21, no. 11, p. 115203, 2010.
[104] C. Xu, D. Niu, N. Muralimanohar, R. Balasubramonian, T. Zhang, S. Yu, et
al., "Overcoming the challenges of crossbar resistive memory architectures,"
in IEEE 21st International Symposium on High Performance Computer
Architecture (HPCA), 2015, pp. 476-488.
[105] C. Ho, C.-L. Hsu, C.-C. Chen, J.-T. Liu, C.-S. Wu, C.-C. Huang, et al., "9nm half-pitch functional resistive memory cell with < 1 μA programming current using thermally oxidized sub-stoichiometric WOx film," in Electron Devices
Meeting (IEDM), 2010 IEEE International, 2010, pp. 19.1.1-19.1.4.
[106] S. Pi, P. Lin, and Q. Xia, "Cross point arrays of 8 nm× 8 nm memristive devices fabricated with nanoimprint lithography," Journal of Vacuum
Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, vol. 31, no. 6, p. 06FA02, 2013.
[107] A. Younis, D. Chu, X. Lin, J. Yi, F. Dang, and S. Li, "High-performance nanocomposite based memristor with controlled quantum dots as charge traps," ACS applied materials & interfaces, vol. 5, no. 6, pp. 2249-2254, 2013.
[108] C. Nauenheim, Integration of resistive switching devices in crossbar
structures. Jülich Forschungszentrum, Zentralbibliothek, 2010.
[109] D. B. Strukov and K. K. Likharev, "Defect-tolerant architectures for nanoelectronic crossbar memories," Journal of Nanoscience and
Nanotechnology, vol. 7, no. 1, pp. 151-167, 2007.
[110] K.-T. T. Cheng and D. B. Strukov, "3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applications," in Proceedings of the
2012 ACM international symposium on International Symposium on Physical Design, 2012, pp. 33-40.
[111] P. Lin, S. Pi, and Q. Xia, "3D integration of planar crossbar memristive devices with CMOS substrate," Nanotechnology, vol. 25, no. 40, p. 405202, 2014.
© COPYRIGHT
UPM
193
[112] C. Nauenheim, C. Kugeler, A. Rudiger, R. Waser, A. Flocke, and T. Noll, "Nano-crossbar arrays for nonvolatile resistive RAM (RRAM) applications," in 8th IEEE Conference on Nanotechnology, 2008.
[113] M. Dong and L. Zhong, "Nanowire crossbar logic and standard cell-based integration," IEEE transactions on very large scale integration (VLSI)
systems, vol. 17, no. 8, pp. 997-1007, 2009.
[114] S. Hamdioui, H. Aziza, and G. C. Sirakoulis, "Memristor based memories: Technology, design and test," in Design & Technology of Integrated Systems
In Nanoscale Era (DTIS), 9th IEEE International Conference On, 2014, pp.
1-7.
[115] S. Hamdioui and A. J. Van De Goor, "An experimental analysis of spot defects in SRAMs: realistic fault models and tests," in Test Symposium,
2000.(ATS 2000). Proceedings of the Ninth Asian, 2000, pp. 131-138.
[116] S. Hamdioui, M. Taouil, and N. Z. Haron, "Testing open defects in memristor-based memories," IEEE Transactions on Computers, vol. 64, no. 1, pp. 247-259, 2015.
[117] N. Z. Haron and S. Hamdioui, "On defect oriented testing for hybrid CMOS/memristor memory," in Test Symposium (ATS), 2011 20th Asian, 2011, pp. 353-358.
[118] N. Z. Haron and S. Hamdioui, "DfT schemes for resistive open defects in RRAMs," in Design, Automation & Test in Europe Conference & Exhibition
(DATE), 2012, pp. 799-804.
[119] P. J. Kuekes, W. Robinett, G. Seroussi, and R. S. Williams, "Defect-tolerant interconnect to nanoelectronic circuits: internally redundant demultiplexers based on error-correcting codes," Nanotechnology, vol. 16, no. 6, p. 869, 2005.
[120] D. B. Strukov and K. K. Likharev, "CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices,"
Nanotechnology, vol. 16, no. 6, p. 888, 2005.
[121] C. J. Xue, Y. Zhang, Y. Chen, G. Sun, J. J. Yang, and H. Li, "Emerging non- volatile memories: opportunities and challenges," in Proceedings of the
seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, 2011, pp. 325-334.
[122] A. Chen, "A comprehensive crossbar array model with solutions for line resistance and nonlinear device characteristics," IEEE Transactions on
Electron Devices, vol. 60, no. 4, pp. 1318-1326, 2013.
[123] S. Shin, K. Kim, and S.-M. Kang, "Analysis of passive memristive devices array: data-dependent statistical model and self-adaptable sense resistance for RRAMs," Proceedings of the IEEE, vol. 100, no. 6, pp. 2021-2032, 2012. [124] M. A. Zidan, "Memristor circuits and systems," Ph.D. dissertation,
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division, King Abdullah University of Science and Technology, Kingdom of Saudi Arabia, 2015.
[125] D. Niu, C. Xu, N. Muralimanohar, N. P. Jouppi, and Y. Xie, "Design trade- offs for high density cross-point resistive memory," in Proceedings of the
2012 ACM/IEEE international symposium on Low power electronics and design, 2012, pp. 209-214.
© COPYRIGHT
UPM
194
[126] Y.-X. Chen and J.-F. Li, "Fault modeling and testing of 1T1R memristor memories," in VLSI Test Symposium (VTS), IEEE 33rd, 2015, pp. 1-6.
[127] W. Wu, S. Brongersma, M. Van Hove, and K. Maex, "Influence of surface and grain-boundary scattering on the resistivity of copper in reduced dimensions," Applied physics letters, vol. 84, no. 15, pp. 2838-2840, 2004. [128] G. H. Kim, K. M. Kim, J. Y. Seok, M. H. Lee, S. J. Song, and C. S. Hwang,
"Influence of the interconnection line resistance and performance of a resistive cross bar array memory," Journal of The Electrochemical Society, vol. 157, no. 10, pp. G211-G215, 2010.
[129] A. Chen, Z. Krivokapic, and M.-R. Lin, "A comprehensive model for crossbar memory arrays," in Device Research Conference (DRC), 70th
Annual, 2012, pp. 219-220.
[130] J. Liang and H.-S. P. Wong, "Cross-point memory array without cell selectors—device characteristics and data storage pattern dependencies,"
IEEE Transactions on Electron Devices, vol. 57, no. 10, pp. 2531-2538,
2010.
[131] C.-L. Lo, T.-H. Hou, M.-C. Chen, and J.-J. Huang, "Dependence of read margin on pull-up schemes in high-density one selector–one resistor crossbar array," IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 420-426, 2013.
[132] J. Y. Seok, S. J. Song, J. H. Yoon, K. J. Yoon, T. H. Park, D. E. Kwon, et al., "A review of three‐dimensional resistive switching cross‐bar array memories from the integration and materials property points of view," Advanced
Functional Materials, vol. 24, no. 34, pp. 5316-5339, 2014.
[133] J. Mustafa, "Design and analysis of future memories based on switchable resistive elements," Ph.D. dissertation, Faculty of Electrical Engineering and Information Technology, RWTH Aachen University, Germany, 2006.
[134] C. Kügeler, R. Rosezin, E. Linn, R. Bruchhaus, and R. Waser, "Materials, technologies, and circuit concepts for nanocrossbar-based bipolar RRAM,"
Applied Physics A, vol. 102, no. 4, pp. 791-809, 2011.
[135] S. Kim, J. Zhou, and W. D. Lu, "Crossbar RRAM arrays: Selector device requirements during write operation," IEEE Transactions on Electron