SC-FDE always requires the full transformation of a block from time-domain to frequency- domain and back. This necessity entails a complexity overhead, which makes SC-FDE appear unfavorable in complexity comparisons between different equalization architectures. How- ever, it is often overlooked that frequency-domain processing offers efficient integration of additional baseband signal processing. Hence, a comparison of the efficiency of different receiver strategies is only useful, if all aspects of the baseband processing are considered. FDE offers a flexible and low-complexity way to filter and resample the received signal. All- digital baseband receiver require over-sampling to perform correct frequency synchronization and maximize the SNR. With a sampling bandwidth larger than the excess bandwidth of the pulse shape filter, the matched filter can be integrated in digital-domain. Unfortunately the over-sampled signal is not suitable for low-complexity detection. Hence, decimation of the received signal before detection is required, which usually entails an additional decimation filter that contributes significantly to the overall power consumption of the receiver [65]. Frequency-domain signal processing provides a flexible way to perform filtering and decima- tion on signals with fractional over-sampling factors.
Frequency-Domain Matched Filter
FD processing allows the simple integration of a matched filter in the baseband processing. Figure 2.19 shows the commonly used RRC pulse shape in time- and frequency-domain with a roll-off factor of 0.2. The pulse shape was generated with an over-sampling factor of 1.25. The frequency-domain representation in Fig. 2.19b shows the symbol bandwidth in yellow, the excess bandwidth of the pulse-shape filter in red and the excess bandwidth of the over- sampling in grey. Synchronization can be performed in digital domain as long as the sampling bandwidth is equal or larger than the excess bandwidth of the pulse. Additional sampling bandwidth can be required to compensate non-ideal filters in the analog frontend. Hence, the exact amount of over-sampling depends heavily on the characteristics of the analog frontend and the required selectivity. From a power-efficiency perspective it is desirable to use the minimal over-sampling rate which fulfills the performance requirements, in order to have the least amount of samples to process. TD receivers [79][72][80] often implement an integer (or half-integer) over-sampling factors to simplify the filter design. SC-FDE architectures allow a very fine-grained selection of the fractional over-sampling as the only requirement for efficient sampling is that the block size
NOS= ROS· N (2.26)
of the over-sampled signal is again integer. This condition implies that the sampling band- width can be adjusted in steps of fspacing= fsymN where fsymbol is the symbol rate. For an
IEEE 802.11ad system, fspacingevaluates to 3.4375 MHz. A comparison to the commonly used
step size of 0.5 fsym = 880MHz underlines the high flexibility of frequency-domain based
filtering.
Another advantage of frequency-domain filtering is the possibility to integrate sampling delays. The sampling point alignment proposed in Section 2.2.2 for optimization of SNR and delay spread can be easily integrated into the matched filter. Fractional shifts of the sampling point can be performed in FD by a frequency dependent phase rotation of the pulse shape coefficients. This can not only be used to establish the optimal initial sampling phase, but also for SFO compensation.
Frequency-Domain Decimation
A fractionally-sampled received signal allows flexible filtering but is not suitable for sym- bol detection. Decimation is required to transform the over-sampled received signal into a symbol spaced sequence. In FD the signal can be decimated by circular folding of the excess bandwidth onto the signal, a technique which is also sometimes called spectral over- lapping [63]. Circular folding is demonstrated for a discrete raised cosine pulse shape in Fig. 2.20. Decimation can be implemented as simple addition of the frequency components. The implementation of the folding operation can take advantage of knowledge about the shape of any preceding pulse filter. Sub-carriers for which the corresponding filter coefficients
Figure 2.20 – Folding of the excess bandwidth of a raised cosine (RC) pulse to symbol-spaced sampling.
are zero can be directly omitted from the folding.
Sampling rate decimation in FD implies that FFT and IFFT operate on different block sizes3. This property can be undesirable in narrowband systems where FFT and IFFT operations share the same physical hardware. In the wideband mmWave systems it is usually not a problem as dedicated hardware is required for FFT and IFFT in order to achieve the necessary throughput.
π/2-rotation Modulation
In FDE-based equalization architectures, theπ/2-rotation Modulation described in Section 2.1.4 can be seen as a cyclic shift in frequency-domain. Hence, theπ/2-rotation can be reverted after decimation by reordering the frequency bins before back transformation to time-domain. The DFT transform pair,
xnej 2πnl/N c s Xk−l, (2.27)
for a complex rotation of the sequence xn, n= 1,...,N-1 and the effect on its DFT Xk, k=
1, ..., N -1 can be used for theπ/2 rotation of the modulation in time-domain. The π/2 rotation 3Several algorithms are known which allow the hardware implementation of non-power-of-two FFTs [81], an
(a) baseline
(b) optimized
Figure 2.21 – SC-FDE based baseband signal processing architectures.
corresponds to a circular shift of the frequency-domain vector by
l=N
4, (2.28)
where N is the length of the DFT vector. The multiplication in TD transforms into a simple memory operation in FD, which can be absorbed in the reordering operations necessary for the decimation and therefore comes with no additional overhead.