1.2 Software para el funcionamiento del HPC
1.2.4 Software para la instalaci´on de aplicaciones de tipo cient´ıfico y la
Unlike their vertical counterpart, the lateral power device has low and high-voltage terminals on the same side of the wafer, and is designed to perform electrical functions only on the very top region (up to 20 μm thick [67]). Ideally speaking, the rest of the wafer should be completely electrical inactive, and serves only as a heat sink and mechanical support during device fabrication and operation. In reality, the wafer will be engineered in a way that the substrate’s electrical interference is minimised or can be manipulated under the specified working conditions. This can bring about a beneficial
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change in one aspect but detrimental change in others. Over the last decade, many Si- based platforms have been developed for power ICs, such as Bulk Si, SOI, Partial SOI (PSOI), Si on thick insulator (SOTI), membrane SOI and Membrane bulk Si (see Fig. 3.3). Some of these structures are free from strong substrate effect, while some have to live with it owing to the presence of built-in PN junction or Silicon-SiO2-Silicon (SOS)
layout.
P-type Si
N-type Si
Si
SiO2 or other dielectric materials
Si
P-type Si SiO2 or Void N-type Si Si SiN passivationSi
SiO2Si
SiN passivationSi
InsulatorFigure 3.3. The Si-based substrates where lateral power devices are fabricated. From left to right, top to bottom, are Bulk Si, SOI, PSOI, Membrane Bulk Si, Membrane
SOI and Si on thick insulator (SOTI).
3.2.1.
Structures with substrate effects
Bulk Si, SOI and PSOI are equipped with either a horizontal PN junction or/and a SOS capacitor (see Fig. 3.3), both for electrical isolation. The PN junction allows heat to escape easily while the SOS capacitor does not, which makes Bulk Si the most thermally conductive among the three. However, the PN structure can react with a device’s n or p type regions and activate parasitic BJTs, which causes bipolar action and injects carriers into the substrate, thereby increasing turn-off losses. Furthermore, the PN junction is not a strong electrical barrier at high temperature, due to a large thermally produced drain-to- substrate leakage current. By contrast, the dielectric isolation (DI) in SOI prevents the substrate’s bipolar effects and offers remarkable device confinement at high temperature. This significantly reduce the power losses in SOI devices in general, which can partially counteract the poor heat transfer ability. Other methods for thermal improvement of SOI includes the flip-chip design [26], replacement of SiO2 with other dielectric materials
such as diamond, SiC or AlN [68, 69, 70], or the PSOI architecture [5]. PSOI permits a combination of the benefits of Bulk Si and SOI, achieving a better trade-off between electrical isolation and heat extraction. An opening is created in the buried layer within
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the active area and can be placed under the drain or source side [71], which results in a substrate effect mainly controlled by a PN junction or SOS capacitor respectively. This partial isolation can suppress some undesirable behaviour but large leakage can still be produced at elevated temperature [72]. To tackle this problem, the opening can be placed out of the active area next to the drain, which increases the chip area but makes the device well-confined [73]. Alternatively, the leakage can be supressed by using p-type SiC as the substrate material instead of Si, which forms Silicon/oxide/Silicon carbide (SiOSiC) [72].
In LDMOSFETs/LIGBTs, the high voltage applied to the drain/collector has to be sustained laterally and vertically. This requires the built-in PN or SOS layout to withstand a drain-to-substrate potential up to the specified blocking voltage. The PN junction has an advantage in this case as the SOS structure supports the applied voltage with only the overlayer and buried oxide. The enhanced depletion in the top Si film can cause premature avalanche breakdown in LDMOSFETs, or punch-through breakdown in LIGBTs. The lack of substrate depletion enlarges the drain-substrate capacitance and lowers the switching speed [74]. Increasing the oxide thickness can raise the blocking voltage and alleviate the substrate effect, but worsen the heat transfer ability and induce wafer warpage [75, 76]. Silicon on double insulator (SODI) [77], PSOI structure and the trenched BOX layer [78] can address this dilemma but formation of such wafers is not as straightforward as that of SOI [79]. The same applies to another type of PSOI where the interrupted oxide is replaced with an air cavity (void), which forms a silicon on nothing (SON) structure and improves the breakdown voltage [80, 81]. However, if the SOI transistor has very a high blocking voltage and limited power rating, self-heating will not be a big issue. One example is the 2000 V SOI LDMOSFET having a 12.2 μm BOX layer, developed for HVIC applications [82]. The SOI structure was prepared by wafer bonding and no warpage problem being reported [82]. Although a thick buried oxide is present in this device, the large chip area required for 2000 V increases the thermal capacitance and cross section for vertical heat transfer. In summary, of the three substrates discussed, the SOI architecture suffers the least from the parasitic effects induced by the substrate at elevated temperatures, despite being weak at heat extraction.
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3.2.2.
Structures without strong substrate effects
Si on thick insulator (SOTI), membrane bulk Si and SOI are constructed to achieve the same goal—the complete removal of substrate effects. The implementation of deep reactive ion etch (DRIE) detaches the Si under the drift and drain/anode region in the two membrane architectures, leaving only a pillar behind under the source for mechanical support [83, 84]. Forming SOTI wafers often involves epitaxial Si growth or a wafer bonding process performed on a bulk insulator, such as sapphire [85] and semi-insulating SiC [14]. As a result, the semi-insulating substrate suppresses any substrate effects on the device and the vertical breakdown limit eased. This allows fast HV LIGBTs to be built on the membrane bulk Si and be free from the back gate MOS effect, preventing the punch-through breakdown [86]. However, the RESURF effect facilitated by the substrate is lost, which lowers the doping allowance in the drift region of traditional LDMOS designs. However, this can be solved by using 3D RESURF technique which depletes the Si layer in the direction of the device width [87].
Compared with the membrane structures, one drawback of the SOTI substrate is the quality of the Si layer. For example, atomic migration can happen during high temperature treatment (e.g. annealing and oxidation) in Si/Diamond and Si/Al2O3, leading to an
amorphous SiC layer sandwiched in-between [88] and a Si film contaminated by Al acceptors from Al2O3, respectively [89]. It has been experimentally proven that Si/(SI)
SiC substrates are compatible with the conventional Si fabrication process [14, 15]. Nonetheless, the Si/SiC wafers have higher cost and less wafer yield at the present time, putting them in disadvantage compared with the membrane structures.
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