Table 8 summarizes the signals that are available as output on any GPIO pin. The CTRLn column shows the configuration value that needs to be written to any one of the GPIOCTRL0-GPIOCTRL5 registers in order to get the described functionality. The IN column in Table 8 shows which command strobe that will be executed if the GPIO is configured as input and an edge (with the correct polarity) is applied. The OUT column shows the name of the internal signal that is observable on the pin if the GPIO is configured as an output.
Table 9: GPIO configuration CTRLn
(hex) IN
(Command strobes)
OUT Description of OUT signal
0x00 SIBUFEX Clock Clock signal. Programmable frequency from 1MHz to 16MHz 0x01 SRXMASKBITCLR RF_IDLE RF_IDLE exception. See Table 14: Exceptions summary for
details.
0x02 SRXMASKBITSET TX_FRM_DONE TX_FRM_DONE exception. See Table 14: Exceptions summary for details.
0x03 SRXON TX_ACK_DONE TX_ACK_DONE exception. See Table 14: Exceptions summary for details.
0x04 SSAMPLECCA TX_UNDERFLOW TX_UNDERFLOW exception. See Table 14: Exceptions summary for details.
0x05 SACK TX_OVERFLOW TX_OVERFLOW exception. See Table 14: Exceptions summary for details.
0x06 SACKPEND RX_UNDERFLOW RX_UNDERFLOW exception. See Table 14: Exceptions summary for details.
0x07 SNACK RX_OVERFLOW RX_OVERFLOW exception. See Table 14: Exceptions summary for details.
0x08 STXON RXENABLE_ZERO RXENABLE_ZERO exception. See Table 14: Exceptions summary for details.
0x09 STXONCCA RX_FRM_DONE RX_FRM_DONE exception. See Table 14: Exceptions summary for details.
0x0A SFLUSHRX RX_FRM_ACCEPTED RX_FRM_ACCEPTED exception. See Table 14: Exceptions summary for details.
0x0B SFLUSHTX SRC_MATCH_DONE SRC_MATCH_DONE exception. See Table 14: Exceptions summary for details.
0x0C SRXFIFOPOP SRC_MATCH_FOUND SRC_MATCH_FOUND exception. See Table 14: Exceptions summary for details.
0x0D STXCAL FIFOP FIFOP exception. See Table 14: Exceptions summary for details. 0x0E SRFOFF SFD SFD exception. See Table 14: Exceptions summary for details. 0x0F SXOSCOFF DPU_DONE_L DPU_DONE_L exception. See Table 14: Exceptions summary for
details.
0x10 DPU_DONE_H DPU_DONE_H exception. See Table 14: Exceptions summary for details.
0x11 MEMADDR_ERROR MEMADDR_ERROR exception. See Table 14: Exceptions summary for details.
0x12 USAGE_ERROR USAGE_ERROR exception. See Table 14: Exceptions summary for details.
0x13 OPERAND_ERROR OPERAND_ERROR exception. See Table 14: Exceptions summary for details.
0x14 SPI_ERROR SPI_ERROR exception. See Table 14: Exceptions summary for details.
0x15 RF_NO_LOCK RF_NO_LOCK exception. See Table 14: Exceptions summary for details.
0x16 RX_FRM_ABORTED RX_FRM_ABORTED exception. See Table 14: Exceptions summary for details.
0x17 RXBUFMOV_TIMEOUT RXBUFMOV_TIMEOUT exception. See Table 14: Exceptions summary for details.
0x18 UNUSED UNUSED exception. See Table 14: Exceptions summary for
details.
... Reserved
0x21 Exception channel A Pin is high when one or more of the exception flags in collection A are active. It is configurable which exceptions to include in collection A.
CTRLn (hex)
IN
(Command strobes)
OUT Description of OUT signal
0x22 Exception channel B Pin is high when one or more of the exception flags in collection B are active. It is configurable which exceptions to include in collection B.
0x23 Complementary exception
channel A
Pin is high when one or more exception flags not in collection A are active.
0x24 Complementary exception
channel B
Pin is high when one or more exception flags not in collection B are active.
0x25 Predefined exception channel
for RX related errors. Predefined exception channel. High when one or more of the following exception flags are active: RX_UNDERFLOW, RX_OVERFLOW, RX_FRM_ABORTED and
RXBUFMOV_TIMEOUT
0x26 Predefined exception channel
for general error conditions. High when one or more of the following exception flags are active: MEMADDR_ERROR, USAGE_ERROR, OPERAND_ERROR and SPI_ERROR.
0x27 fifo Pin is high when one or more bytes are in the RXFIFO. Low
during RXFIFO overflow.
0x28 fifop Pin is high when the number of bytes in the RXFIFO exceeds the programmable threshold or at least one complete frame is in the RXFIFO. Also high during RXFIFO overflow. Not to be confused with the FIFOP exception.
0x29 cca Clear channel assessment. See FSMSTAT1 register for details on
how to configure the behavior of this signal.
0x2A sfd Pin is high when a SFD has been received or transmitted. Cleared when leaving RX/TX respectively. Not to be confused with the SFD exception.
0x2B lock Pin is high when frequency synthesizer is in lock.
0x2C rssi_valid Pin is high when the RSSI value has been updated at least once since RX was started. Cleared when leaving RX.
0x2D sampled_cca A sampled version of the CCA bit from demodulator. The value is updated whenever a SSAMPLECCA or STXONCCA strobe is issued.
0x2E rand_i Random data output from the I channel of the receiver. Updated at 8MHz.
0x2F rand_q Random data output from the Q channel of the receiver. Updated at 8MHz
0x30 rand_xor_ i_q XOR between I and Q random outputs. Updated at 8MHz
0x31 sniff_clk 250kHz clock for packet sniffer data.
0x32 sniff_data Data from packet sniffer. Sample data on rising edges of sniff_clk. 0x33 mod_serial_clk 250kHz serial data clock from modulator.
0x34 mod_serial_data Serial data from modulator. Sample data on rising edges of mod_serial_clk.
... Reserved
0x43 rx_active Indicates that FFCTRL is in one of the RX states. Active high. Note: This signal might have glitches, because it has no output flip-flop and is based on the current state register of the FFCTRL FSM.
0x44 tx_active Indicates that FFCTRL is in one of the TX states. Active high. Note: This signal might have glitches, because it has no output flip-flop and is based on the current state register of the FFCTRL FSM.
... Reserved
0x5E dpu_core_activepri(0) High when the DPU is busy processing a low priority thread. 0x5F dpu_core_activepri(1) High when the DPU is busy processing a high priority thread.
CTRLn (hex)
IN
(Command strobes)
OUT Description of OUT signal
... Reserved
0x62 dpu_state_l_active High when low priority thread is pending or active. 0x63 dpu_state_h_active High when high priority thread is pending or active.
… Reserved
0x7E ‘0’ Constant value
12 Power Modes
CC2520 has three power modes as described below. In all these power modes the supply voltage is applied to the circuit.
In Low Power Mode 2 (LPM2) the digital voltage regulator is turned off (VREG_EN=0) and no clocks are running. No data is retained. All analog modules are in power down state.
In Low Power Mode 1 (LPM1) the digital voltage regulator is on (VREG_EN=1), but no clocks are running. Data is retained. The power down signals to the analog modules are controlled by the digital part.
In Active mode the digital voltage regulator is on (VREG_EN=1) and the crystal oscillator clock is running. The power down signals to the analog modules are controlled by the digital part.