SUMMARYSUMMARYSUMMARY

3.3 Current Current Mirrors Mirrors

3.3.1

3.3.1 Basic Basic Mirror Mirror Operation

Operation

The objective of a current mirror is to duplicate its input current at its output, irrespective of the output voltage present. To do this without errors, two transistors must match and all their respective port-to-port voltages must equal. However, since collector-emitter and drain-source voltages v_CE and v_DS have minimal impact on collector and drain currents i_Cand i_D in the transistors’ high-gain mode (i.e., for-ward active or slightly saturated for BJTs and saturation for FETs), v_CE and v_DSneed not equal for their currents to match reasonably well, as long as v_BE’s and v_GS’s equal. For example, short-circuiting the base-emitter and gate-source control terminals of matched transistors, as shown in Fig. 3.1a and b, and ensuring their respective collector-emitter and drain-source voltages are sufficiently high, produce an output current that is approximately equal to its input:

i I v Connecting the input transistor ’s collector (or drain) to the base (or gate) ensures the input current charges the parasitic base-emitter (or gate-source) capacitance until the collector (or drain) current is equal to input current i_IN, at which point the capacitor stops charging

i_o1

FIGUREIGURE3.183.18 Common-mode equivalent half circuit.

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Chapter ThreeChapter Three

and v_BE(or v_GS) is set. Because connecting the collector and base termi-nals amounts to using the BJT as a base-emitter pn-junction diode, Q_INand M_INin Fig. 3.19a and b are said to be diode connected.

This mirror configuration is also useful for amplifying or attenuat-ing a current by a constant factor because changattenuat-ing the number of transistors in the input and/or output of the circuit modifies the cir-cuit’s input-output gain ratio. For instance, using three matched paral-lel transistors in the input equally splits input currenti_INinto three and using two matched parallel transistors at the output ensures the frac-tional current flowing through each input device (i.e.,iC= iIN/3) flows through each output device, yielding a sum total of 2i_Cor 2i_IN/3, as depicted in Fig. 3.20a. This mirror configuration mimics the effects of having an input transistor with 3 times the minimum emitter area and an output device with 2 times the minimum emitter area. The same idea applies to MOSFETs, except gain is set by width-length aspect ratios (i.e., W /L), as illustrated in the 2× mirror shown in Fig. 3.20b.

Performance Performance

Important metrics of a current mirror include its accuracy, input and output voltage limits, input and output resistances, gain, and band-width. To start, with respect to accuracy, base currents in BJTs subtract a fraction of the input current flowing into the mirror. In the case of a one-to-one npn mirror, for example, bases pull and subtract two base

(a) (b)

i_OUT i_IN

M _O M _IN

V _DS>V _DS(sat) i_OUT

i_IN 2i _B

Q_O Q_IN

V _CE>V _CE(min)

F

FIGUREIGURE3.193.19 Basic (a a ) npn and (b b ) n-type MOS current mirrors.

(a) (b)

i_OUT= 2i_IN /3 i_IN

i ^C i = ^{I N} / 3

i ^C i = ^{I N} / 3

A = 2x A = 3x

i_OUT= 2i_IN i_IN

2W / L W / L

F

FIGUREIGURE3.203.20 Nonunity (a a ) BJT and (b b ) MOSFET current mirrors.

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currents (i.e., 2i_B) from input current i_INand consequently cause the output (which is a collector) to sink a lower current (i.e.,i_OUT< i_IN),

i i i i _IN

≈ + ≈

_{C B}

+

_Ci

⎛

_OUT

⎝ ⎜ ⎞

⎠ ⎟ = ⎛ +

⎝ ⎜ ⎞

⎠ ⎟

2 1 2

1 2

β β

^(3.67)

where i^Bis the base current into Q^INand Q^O in Fig. 3.19 a. Slightly increasing the base-emitter voltage of output transistor Q_Owith an ohmic voltage drop increases its collector current, partially compen-sating for the mirror’s

β

error, as illustrated in Fig. 3.21 a. Since the collector’s current variation

Δ

i_OUTis the result of a small change in its base-emitter voltage

Δ

v_BE, equating resistor voltage v_Rto the lin-ear first-order transconductance (i.e., g_m) translation of the error current (i.e., Ni_B, where N is the effective number of bases attached carrying equivalent input currents) compensates the mirror error to first order:

Δ

i _OUT

= ≡

Ni _B v g

Δ = =

_{BE m} v g _{R m} i R g(_{B β}) _m (3.68)

or

R N

g

NV

m I

β

≡ ≈

t IN

(3.69)

where I _INis the dc value of input current i_IN.

Alternatively, while placing a series

β

-helper BJT level shifter in the collector-base connection path, as shown in Fig. 3.2b, decreases the error current by a factor of

β

, a series MOSFET (Fig. 3.21c) alto-gether eliminates it, given the latter carries no gate current. The pur-pose of the load resistor attached to the

β

-helper transistor, by the way, is to establish a bias current that pushes the pole associated with

(b) (c)

(a)

i_OUT

i_OUT i_OUT

i_IN

i_IN i_IN

2i _B ²i _B

– i _B R_β +

β

F

FIGUREIGURE3.213.21 Basic npn current mirrors with (a a )β-compensating resistor, (b b ) npnβ-helper, and (c c ) MOSβ-helper.

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Chapter ThreeChapter Three

that node to high frequencies. In any case, the simplicity of the

β

-compensating resistor often offsets its relatively poorer accuracy, given its resistance cannot easily track or adjust to a changing input current i_IN.

As already mentioned, all port-to-port terminals in the mirror cir-cuit must equal (i.e., all base- and collector-emitter and gate-, drain-, and bulk-source voltages equal) to produce a quasi-perfect replica of the input current at the output. The collector-emitter and drain-source voltages in the basic current mirror, however, do not match, and although their effects are minimal, they still induce a gain error that is the result of base-width and channel-length modulation effects:

A i

where A_I refers to the mirror gain of each equally sized transistor seg-ment in the current mirror, which would otherwise be 1. For instance, the v_CE-induced systematic gain error of a basic mirror with its output at 3 V and an Early voltage V _Aof 50 V, assuming a base-emitter volt-age of 0.7 V, is approximately 4.3%, excluding random mismatch errors between supposedly matched transistors.

The input and output voltage limits for which the mirror main-tains its prescribed gain is also important. Ideally, the input and out-put voltages should reach both positive and negative supplies without significant impact on the output current. However, the input voltage in a basic current mirror is one base-emitter voltageV _BEor gate-source voltage V _GSfrom ground, which can be on the order of 0.55–1.5 V, depending on process, size, temperature, and current density.

β

-helper transistors unfortunately increase the overhead by anotherV _BEor V _GS, unlike

β

-compensating resistors, which are relatively benign to the circuit in this respect, albeit with poorer accurate. The voltage over-head associated with the output is the lowest voltage the output transistor can tolerate across its collector-emitter or drain-source terminals without significantly altering its output current, which cor-responds to deep saturation limitV _CE(min)or saturation voltage V _DS(sat) (e.g., 0.2–0.5 V).

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Small-Signal Response at Low Frequency Small-Signal Response at Low Frequency

When considering the small-signal gain of the circuit, accounting for the effects of the source and load is important. Before including these effects, however, it is best to simplify the circuit where possible. To this end, Fig. 3.22a illustrates the complete small-signal equivalent circuit of the basic npn current mirror shown in Fig. 3.19 a and Fig. 3.22b shows its simplified but loaded counterpart. In diode-connecting input transistor Q^IN, for instance, the equivalent resistance into Q_IN’s transconductor g_m.IN becomes 1/ g_{m. M} because the current flowing through the diode-connected device is linearly proportional to its own terminal voltages. As such, the input resistance of the circuit (i.e., R_IN) reduces to 1/ g_m.IN, the lowest resistance in the parallel combination that R_IN comprises, which also includes base-emitter resistors r_π.INand r_π.Oand Q_IN’s output resistance r_o.IN:

R r r r

g g

O o

m m

IN IN IN

.IN .IN

=

_{π .} ||_π. || _. || 1

≈

1

(3.72)

Base-collector capacitor C_μ also disappears in the simplified circuit because its two terminals are short-circuited, which means C_μ’s dis-placement (i.e., ac) current is zero (i.e., C^μproduces no effects in the

2 C ^π C µ

v ^{i n} g ^m

v_in v_out

r _o R_S

i_s

i ^{L o}

d a

R ^L

o a d ^LC

o a d

Z _IN Z _OUT

r π C π C µ

i_out

r _o

Q_IN i_in

v ^{b e} g ^m

r π C π

C µ r _o

Q_O v ^{b e}

g m

(a)

(b)

F

FIGUREIGURE3.223.22 (a a ) Complete and (b b ) simplified (but loaded) small-signal model of a basic npn current mirror.

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Chapter ThreeChapter Three

circuit). The output of the circuit remains intact and output resistance R_OUTreduces to Q_O’s r_o, the only resistance present.

Perhaps the more meaningful definition of the small-signal gain of the mirror is the translation of source currenti_sto load current i_Loadin the presence of source resistanceR_Sand load capacitanceC_Loadbecause both R_Sand C_Loadrepresent realistic operating conditions. As discussed

earlier in this chapter, decomposing the signal path into its equivalent current-voltage and voltage-current translations and using the results obtained in the single-transistor section helps ascertain the gain across the circuit. In this case, small-signal low-frequency current gain A_{I .LF}is the product of small-signal translationsi_s to input voltage v_in, v_in to transconductor currenti_gm, i_gmto output voltagev_out, and v_outto i_Loador

A i

assuming a one-to-one area ratio between the matching transistors (i.e., g_m.INequals g_m.O). Note that a gain of 1 only results when R_INis considerably smaller than R_S and R_OUT larger than R_Load; in other words, ideal input and output resistances R_INand R_OUT, respectively, approach zero and infinitely high values.

Small-Signal Response at High Frequency Small-Signal Response at High Frequency

The operation described thus far assumes steady-state conditions and therefore relates to low frequency only. To ascertain the high-frequency response of the circuit, it is usually easier to start at low frequencies and find the poles that exist as frequency increases, short-circuiting the capacitor that produced poles at lower frequencies.

Before analyzing the circuit, though, as noted earlier, Q_IN’s C_μ.IN is short-circuited (Fig. 3.22a) so no ac voltage exists across its terminals and consequently no ac current results through the device, which means, for all practical purposes, C_μ.INdoes not exist.

Noting R_INis generally low and R_OUTis high reveals output pole p_O precedes input pole p_INas frequency increases. As a result, with respect to dominant pole p_O, loading capacitor C_Loadand C_μsteer cur-rent away from the output when their collective impedance is equal to or smaller than their equivalent parallel resistance (i.e., r_o||R_Load).

Because the base terminal side of C_μis at a low-resistance point (i.e., 1/ g_m from ground), its associated series impedance has negligible

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effects on the total capacitor impedance so p_Ooccurs when both C_Load and C_μ shunt r_o||R_Load:

As frequency increases past p_O, assuming C_Loadis dominant, C_Load becomes a short circuit and Q_IN’s C_π.INand C_μ.INand Q_O’s C_π.Obegin to shunt and steer current away from Q_IN’s base, decreasing input volt-age v_inand the output current it produces in transistor Q_O(i.e., i_out).

The Miller effect of C_μ.INis low because p_O, at this point, decreased much of Q_O’s CE gain, which also means v_outis a low-impedance node (to ac ground). As a result, the effects of input (mirror) pole p_INoccur when equivalent input capacitance C_IN(or C_π.IN, C_μ.O, and C_π.O) shunt the parallel combination of R_INand R_S:

1 1

Capacitor C_μor C_GD, as in the CE/CS transistor case, also consti-tute an out-of-phase feed-forward path whose effects prevail at and above frequencies where the capacitor current is equal to or greater than the mirroring transconductor current. Input pole p_INprecedes this right-half-plane zero (i.e., z_RHP), which resides at g_m/2πC_μ or g^m/2πC^GD, because the parasitic capacitance associated with the for-mer exceeds the latter. It is important to keep z_RHPwell above frequen-cies of interest because its right-half-plane effect not only extends bandwidth to problematic frequency regions, where several parasitic

poles reside, but also decreases phase in the process.

3.3.2

3.3.2 Cascoded Cascoded Mirror Mirror Operation

Operation

The objective of the cascoded mirror with respect to its basic counter-part is twofold: (1) improve mirroring accuracy and (2) decrease sen-sitivity to variations in output voltage (i.e., increase output resistance).

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Chapter ThreeChapter Three

The idea is to eliminate base-width and channel-length modulation effects in the mirroring devices by forcibly equating their respective collector-emitter or drain-source voltages with cascode transistors.

Because cascode devices (e.g.,Q_CINand Q_COor M_CINand M_COin Fig. 3.23a and b) carry the same current density, their base-emitter or gate-source voltages and therefore their emitter or source voltages equal (e.g.,Q_IN’s and Q_O’s collector-emitter voltagesv_CE’s equal), eliminating all modu-lation effects. Sincev

CE’s orv

DS’s are equal tov

BEorv

GSwith respect to ground, variations in the output voltage have minimal impact on the port-to-port voltages of the mirroring devices (e.g.,Q_INand Q_Oor M_IN and M_O), producing little effects in output currenti_OUT, that is to say, increasing the output resistance of the mirror.

Performance Performance

As in the basic mirror, base currents degrade the accuracy perfor-mance of cascoded mirrors and

β

-compensation resistors and

β

-helper transistors help reduce those effects. Unlike the basic mirror, however, base-width and channel-length modulation effects on the mirroring

devices are less prevalent, although random, process-induced mis-match errors remain. Unfortunately, eliminating the modulation errors increases the input and output voltage requirements of the circuit. For instance, in the case of the cascoded mirrors in Fig. 3.23a and b, the dc input voltage is the voltage across two diode-connected devices (i.e., 2V _BEor 2V _GS) and its output must exceed the diode-connected voltage impressed across the output mirroring device by one collector-emitter or drain-source voltage (i.e.,V _BE+ V _CE(min)or V _GS+ V _DS(sat)).

Relaxing the input and output headroom requirements of the cascode circuit amounts to eliminating the dc voltage effects of the cascode transistors. For instance, disconnecting the bases or gates of the cascodes from the circuit and appropriately biasing them one base-emitter or gate-source voltage above one saturation voltage, as in Fig. 3.24a and b, continues to equate the v_CE’s or v_DS’s across the

(a)

i_OUT i_OUT

i_IN i_IN

(b) V _OUT>V _BE+V _CE(min) V _OUT >V _GS+V _DS(sat)

Q_O

Q_IN M _IN M _O

Q_CO

Q_CIN M _CIN M _CO

V _CE.IN=V _CE.O V _DS.IN=V _DS.O F

FIGUREIGURE3.233.23 (a a ) NPN- and (b b ) NMOS-cascode current mirrors.

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mirroring devices (although now at V _CE(min)or V _DS(sat)) while avoiding their V _BEor V _GSimpact on headroom. The input voltage is therefore back to what it was in the basic current mirror, at one V _BEor V _GS above ground, but its output must now exceed two minimum satu-ration voltages, which is higher than in the basic mirror but lower than in the simple cascode version shown earlier. Note that generat-ing the bias voltage requires additional circuit, silicon real estate, and power. In the sample BJT embodiment shown in Fig. 3.24a, for example, the resistor shifts up a base-emitter voltage by only the minimum collector-emitter voltage a BJT can sustain before entering the deep saturation region. Similarly, the aspect ratio (i.e., W /L) of biasing transistor M_X(and/or its biasing current) in the MOS exam-ple shown in Fig. 3.24b is sufficiently low to ensure its saturation voltage is large enough to accommodate the saturation voltage in the gate-source voltage of the cascode device (e.g., V _DS2(sat)) and ensure the voltage across the mirroring transistor is above its saturation point (e.g., V _DS1(sat)):

V V V _GSX

= +

_{T DSX sat}V V

≡ +

_{( ) GS2}

= +

V V _{DS sat1( ) T DS sa2( tt)}

+

V _{DS sat1( )} (3.76) or

V _{DSX sat( )}

≡

V _{DS sat1( )}

+

V _{DS( sat2 )} (3.77) Small-Signal Response at Low Frequency

Small-Signal Response at Low Frequency

Figure 3.25 presents the complete and simplified but loaded small-signal equivalent circuits of the cascoded mirror circuit, which amount to two diode-connected devices on the input and a CE cascode

(a) (b)

V _OUT> 2V _DS(sat) V _OUT> 2V _CE(min)

V _GS2+V _DS1(sat)

V _BE+V _CE(min) V ^C

E ( m i n )

(W / L)_X< (W / L)_l

M ₁ M ₂ M _X

V _GSX – +

– +– + V _BE

F

FIGUREIGURE3.243.24 (a a ) NPN and (b b ) NMOS low-voltage cascode current mirrors.

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Chapter ThreeChapter Three

transistor degenerated with a CE transistor on the output. Transistors Q_INand Q_Oconstitute a basic mirror and they therefore simplify to the small-signal equivalent circuit shown in Fig. 3.22 b and again in Fig. 3.25b. Similar to the mirror, the current flowing through QCIN’s base-emitter resistance r_π.CINand output resistance r_o.CINare negligibly smaller than their transconductor counterpart, whose equivalent resistance is 1/ g_m, so their effects, for all practical purposes, disap-pear in the simplified small-signal circuit. Q_CIN’s base-collector capac-itor C_μalso disappears because there is no voltage across it to induce a current. As always, r_π’s disappear and v_gs, C_GS, C_GD, and r_dsreplace v _be, C_π, C_μ, and r_o, respectively, in the MOS case.

The input resistance (i.e.,R_IN) of the circuit is the parallel combina-tion of the resistance into the two diode-connected devices and the resistance into the base of output cascode transistorQ_CO. The resis-tance Q_COpresents, however, is considerably higher than the two 1/ g_m

C π C π

C µ C µ

r π

r π v ^{b e}

g ^m

v ^{b e} g ^m

r _o r _o

i_OUT i_IN

Q_CIN Q_CO

(a)

(b)

Q_IN Q_O

Q ^C

I N ^CQ

O

M i r r o r

i ^{L o}

d a

v_in v_out

r o R_S

i_s

R ^L

o a d C ^L

o a d

Z _IN Z _{IN. CO} Z _OUT

C π C µ

r π ^{b e}v g ^m

r _o

r π C π C µ

v ^{b e} g ^m

r _o

2C π C µ

C µ C π C π

r π

v ^{b e} g ^m

v ^{b e} g ^m

1 / g ^m 1 / g ^m

r _o

F

FIGUREIGURE3.253.25 (a a ) Complete and (b b ) simplified (but loaded) small-signal equivalent circuits of the cascode current mirror.

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resistances associated with the diode-connected devices because of the degenerating effects mirroring output resistancer_o.Mhas on Q_CO. As a result, Q_COintroduces a

β

-translation ofr_o.Mto the input, reducing R_INto roughly 2/ g_m:

where r_πdisappears and

β

approaches infinity in the MOS case.

The degenerating effects of r_o.Mon Q_COalso manifest themselves in the output resistance of the circuit (i.e., R_OUT), except r_o.Mis not the only degenerating factor. In fact, Q_CO’s base-emitter resistance r_π.CO, the diode-connected devices (2/ g_m), and the mirror’s output trans-conductor g_m.Mpresent another resistance at Q_CO’s emitter. Because the bottom devices constitute a current mirror, output mirror transis-tor Q_Osinks a mirrored version of the base current flowing through output cascode device Q_CO(i.e., i_gm.O

≈

i_rπ.CO), which means the total emitter-degenerating current is twice Q_CO’s base current and r_o.M’s smaller current contribution, which means the equivalent emitter degenerating resistance is approximately r^π/2:

R v

where R_DEG.COis Q_CO’s effective degenerating resistance, i_π.COis Q_CO’s base current, i_gm.Ois Q_O’s transconductor current, and i_o.Ois the cur-rent flowing through ro. M(which is considerably smaller than iπ.CO).

Note that in the MOS case r_πdisappears and i_π.COis zero so degener-ating resistance R_DEG.COreduces to r_ds.O. In any case, the degenerated output resistance of the circuit is relatively large at approximately R_DEG.COr_o.COg_m.CO,

R _OUTr R

= +

_{o .CO}

+

_DEG.COR r g _DEG.CO

≈

R _{o .CO m.CO DEG.COO}r _{o .CO}g_m.CO (3.80) where R_DEG.COand R_OUTare 0.5r_πand 0.5

β

r_ofor BJTs and r_dsand r_ds² g_m for MOSFETs. Note R_OUTwould be infinitely large if base-width and channel-length modulation effects (i.e., differences inv_CEand v_DS) were

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Chapter ThreeChapter Three

nonexistent, yetR_OUTfor the cascode circuit, whose purpose is to elim-inate these effects, is finite. The reason for this finite value is that changes in v_OUTinduce small variations in thev_CEor v_DSof the bottom output mirror device via the modulation effects of the cascode, thereby introducing v_CEor v_DSdifferences between the mirroring transistors.

Because cascode devices Q_CIN and Q_CO simply channel current into and out of a basic mirror, the low-frequency small-signal current gain of the circuit (i.e., A

I .LF) is roughly the same as that of the basic mirror, except with mitigated (but not completely eliminated) base-width and channel-length modulation effects. To fully comprehend all loading effects, however, source and loading resistances are included in the analysis and the current gain is defined as the transla-tion of source current i_sto load current i_Load. As such, low-frequency current gain A_I.LFis the product of its constituent small-signal transla-tions: i_sto v_in, v_into mirror’s base voltage v_b.M, v_b.Mto mirror’s output transconductor current i_gm.M, i_gm.Mto Q_CO’s emitter voltage v_e.CO, v_e.COto Q_CO’s transconductor current i_gm.CO, i_gm.COto v_out, and v_outto i_Loador As with any mirror, input and output resistances R_INand R_OUTshould

I .LF) is roughly the same as that of the basic mirror, except with mitigated (but not completely eliminated) base-width and channel-length modulation effects. To fully comprehend all loading effects, however, source and loading resistances are included in the analysis and the current gain is defined as the transla-tion of source current i_sto load current i_Load. As such, low-frequency current gain A_I.LFis the product of its constituent small-signal transla-tions: i_sto v_in, v_into mirror’s base voltage v_b.M, v_b.Mto mirror’s output transconductor current i_gm.M, i_gm.Mto Q_CO’s emitter voltage v_e.CO, v_e.COto Q_CO’s transconductor current i_gm.CO, i_gm.COto v_out, and v_outto i_Loador As with any mirror, input and output resistances R_INand R_OUTshould

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