MLC storage is one of the promising feature of PCM which made it attractive among its competitors. With a thorough understanding of the thermoelectric at the active region, it is clear that thermoelectric effects play a critical role in determining the hotspot location within the new device. The size and the location of the hotspot determine the attainable resistance levels and hence directly influence the MLC operation.
3.6. Novel device design using thermoelectrics 26 28 30 32 34 36 38 40 400 450 500 550 600 Distance (nm) Temperature (K) 0 5 10 15 20 25 30 35 40 45 50 500 1000 1500 2000 Distance (nm) Temperature (K) Proposed device Mushroom device GST cell-1 cell-2 GST T iN/SiO 2 T iN/SiO 2 T iN/SiO 2 SiO2 SiO 2 Proposed device Mushroom device cell-2 GST (a) (b)
Figure 3.24: Comparison of the thermal profile attained at the neighboring cells for the mushroom device and the proposed device. From the latter, there is 6%-8% temperature reduction at the GST boundary of the adjacent device.
Recently, Kim et al. proposed a novel device-design approach to address the resistance drift phenomenon. They demonstrated a six-fold decrease in the drift coefficient values of high- resistance states by using a metallic surfactant (metal nitride) layer as an alternative read current path to the amorphous region [Kim et al., 2013]. The idea is to decouple the amorphous regions, which are prone to resistance drift, from the read current path.
The thermoelectric physics can be used to control the location of the hotspot within the phase-change material. By having a additional metallic surfactant layer to have alternate current path to determine the resistance during the readout operation. I propose a new device design as illustrated in the Fig. 3.25.
Chapter 3. Thermoelectric model validation and novel device design
GST
Si
3N
4P
1TiN
TiN
TiN
TiN
GST
GST
Si
3N
4Si
3N
4TiN
TiN
P
1P
1P
2P
2P
2Figure 3.25: (a) Hotspot location without considering any thermoelectric effects. (b) Location of the hotspot with thermoelectric effects for positive applied bias. (c) Applied negative polarity with thermoelectric effects.
The idea is to have two different metallic projection layers with different resistivities (P1 and P2) surrounding the phase-change material towards the top and the bottom electrodes in the conventional confined-cell geometries. The projection layers, P1 and P2, are chosen such that their conductivities lie between those of the crystalline and the amorphous state (ρcr y> ρP 1> ρP 2> ρamo).
For such a symmetrically confined cell, based on the polarity of the applied programming voltage, the location of hotspot will be either closer to the bottom electrode (positive bias) or the top electrode (negative polarity). The read current can therefore be decoupled from the amorphous phase-change material and made to flow through either the P1 or P2 layer, providing distinct resistances according to their conductivities. Depending on the resistivity of the projection layer (P1 and P2), different intermediate resistance states can be attained for the applied bias.
The proposed design is mainly focused on the confined-type devices for two reasons. (a) In the mushroom-type devices, although there is a difference in efficiency between programming with the positive and the negative bias, there is no significant (very minimal) movement of the hotspot. (b) The confined-type device is the new device topology, which is currently being explored owing to its simplicity and its amenability to scaling.
In a phase-change memory, currently multiple levels are stored by applying pulses of varying amplitudes ( or varying duration of trailing edges), so as to program the cell at various interme- diate resistive states. Unlike the mushroom-type devices, in the state-of-the-art confined-cell design, the opposite bias polarities have minimal impact on device operation owing to the symmetry of the device. However, in the novel device design, the thermoelectric effect can be used to store information in the intermediate resistance levels just by programming with the negative-bias voltages.
3.7. Summary 150 200 250 300 350 400 450 103 104 105 106 107 Programming power (μW) Resistance ( ) Negative bias Positive bias
Figure 3.26: Resistance vs. programming power for different applied bias voltage. Different intermediate resistance levels are attained for the same applied programming power with opposite polarity.
3.7 Summary
The proposed comprehensive thermoelectric model has been completely validated with actual experimental device measurements. It was shown that the model can accurately capture the exact device operation under wide range of ambient operating temperatures. The model was simple to implement and could provide numerous insights for understanding the thermal and the electrical transport mechanism in the active region of the device. Therefore, the model was instrumental in studying the influence of various factors (material properties, boundary conditions, etc. ) on device operation. The model can thus be used as a powerful tool to fine-tune the material properties, device geometry and design, in order to maximize device performance and improve its efficiency.
Apart from the knowledge about the thermal distribution within the device, the compact electro-thermal model is a simple but powerful tool for a quick and reasonably good estimate of the temperatures attained within the highly dense PCM array, which otherwise would be a time-consuming and complex task to perform in FEM-based simulations. The thermoelectric model provided information on the thermal profile within the device with such a precision that it provided numerous insights into the device operation. In contrast, the electro-thermal model provides fast and reasonably accurate estimates of the temperatures attained outside the device in dense memory arrays, where precision is not critical. Both models in combination can be used as a powerful tool to completely understand the thermal landscape attained within a PCM array.
Chapter 3. Thermoelectric model validation and novel device design
At the end, I also presented two novel device designs derived from the understanding of the thermoelectric effects. I believe that ideas like these, although basic and far from actual implementation, will pave the way in the right direction for resolving future scalability issues which one can already foresee in terms of PCM scalability.
Contributions:
• Calibration and validation of the thermoelectric model implemented by comparison of the simulation results with the experimental measurements.
• Based on the valuable insights obtained from the thermoelectric model, a thorough investigation on the bias-polarity-dependent behavior of the mushroom-type de- vices was performed.
• Conceived and developed the compact electro-thermal model for a quick estimate of the thermal distribution in dense PCM arrays.
• Proposed novel device design ideas using the thermoelectric insights into device op- eration to tackle the thermal disturb phenomenon and to increase the memory den- sity through MLC capability.
4
Multilevel-Cell Phase-Change
Memory: Circuit architectures
From the aggressive, Flash-dominated non-volatile memory market, one can easily predict that all possible directions for improving the effective density will be exploited. One promising, but challenging direction is the MLC (Multi-level Cell) storage approach, where more than 1 bit of information is stored in each cell. High memory density leads to more functionality, and is currently in huge demand because of the proliferation of big-data storage applications. It has been argued that 2-bits/cell storage and read/write access times in the 100 ns to 1μs range are required to establish PCM as a tier in the memory hierarchy, somewhere between DRAM and Flash memory [Freitas and Wilcke, 2008]. Researchers have already demonstrated the feasibility of MLC in PCM technology [Close et al., 2013; Papandreou et al., 2011].
In this chapter, the process of achieving MLC capability in PCM devices and its characteristics are described. Although there is a wide contrast between the SET and RESET states, there are various factors that limit the practical realization of MLC in PCM. Resistance drift and array variability are the predominant factors affecting reliable MLC storage. Various MLC-enabling technologies are currently being explored to improve the drift resilience. One such approach is the extraction of non-resistance cell-state-based metrics. To reduce array-variability, in general, iterative programming schemes are used to program the intermediate resistance levels. Drift-immune readout metrics are described, followed by the CMOS implementation of novel readout architectures for the extraction of such metrics.
This chapter is organized as follows: Section 4.1 explains MLC operation and characteristics in PCM. Section 4.2 describes the various factors limiting reliable MLC operation. Section 4.3 presents several novel technologies that enable reliable MLC storage, including the novel drift- resilient readout metrics. Section 4.4 explains the MLC programming and readout architecture implemented in CMOS technology. Finally, in Section 4.5.2.4, the chip characterization results of one of the readout extraction scheme is presented.
Chapter 4. Multilevel-Cell PCM: Circuit architectures
4.1 Multilevel Cell storage
Recently, it has been demonstrated that the memory capacity/density of PCM can be increased further by storing more than one bit of information per memory device [Bedeschi et al., 2009], typically known as multi-level cell (MLC) storage. It is one of the prominent features of phase- change memory that renders PCM even more attractive among the emerging non-volatile memory technologies.
The MLC strategy is to make use of the intrinsic capability of the memory device to store analog data to encode more than 1 bit of information per device. In the case of PCM technology, the large resistivity contrast exhibited by these materials between the crystalline and the amor- phous state (typically 3–4 orders of magnitude) and hence the high ON/OFF ratio achieved favor the possibility of storing information in the intermediate resistance states. Figure 4.1 illustrates the typical current vs. voltage (I−V ) characteristics of these devices measured at room temperature. Apart from the extreme RESET (high-resistance) and SET (low-resistance) states, additional information can be stored in any of the intermediate resistance levels.
0 0.5 1 1.5 2 109 108 107 106 105 104 103
Voltage (V)
Current (A)
RESET
SET
Intermediate
states
Figure 4.1: Experimentally measured current vs. voltage (I− V ) characteristics of typical PCM devices at room temperature. Not only the extreme SET and RESET states,but also the intermediate resistance levels can be used to store information.
The intermediate resistance states can be attained by properly modulating the electrical pulses used to program the PCM. Two such pulses are shown in Figure 4.2. By carefully controlling these pulses, one can fine-tune the target analog resistive level of the device, thus paving the 90