Individual subdetectors use either Trip-T (Trigger Pipeline and Timing Chip) or AFTER (ASIC For TPC Electronics Readout) electronics to read out data. AFTER is used in the TPC and the FGD, Trip-T electronics in all other subdetectors. Data collected by Trip-T electronics is sent to a RMM (Readout Merger Module). An RMM controls up to 48 TFBs (Trip-T Frontend Board), which hold Trip-T chips [18], sending run specific parameters and controlling the startup and stopping of TFBs. TFB firmware can also be updated via a RMM. Once a trigger has been received by a RMM it will collect the data from each TFB and pass it to a FPN (Front-end Processing Node). Data are sent by the FPN for storage and offline analysis. Timing and trigger information is sent to the RMM via a SCM (Slave Clock Module) of which there is one for each subdetector using the Trip-T electronics. During full ND280 running the
SCM passes through information from the MCM (Master Clock Module). It can generate its own timing signals, allowing each subdetector to run its own testing and/or calibration. The MCM manages the timing and triggering of the ensemble of ND280 subdetectors during full running. It receives a signal from the GPS system to synchronise beam triggers with the global T2K experiment as well as manage other triggers from within ND280, such as the cosmic trigger [18].
Trip-T Electronics
Trip-T is used in all subdetectors except for the tracker, which demands a very high time resolution. The ASIC (Application Specific Integrated Circuit) was originally designed for the D0 experiment [73]. A Trip-T chip has 32 channels and a 48 channel pipeline to store analogue signals from the MPPCs. The charge is stored in a capacitor before being digitised. The time over which charge is allowed to accumulate before being read out is called the integration period, typically of order 500 ns. A total of 23 integration periods worth of data can be stored per channel. This means that when a trigger is received data is read out covering a few microseconds depending on the selected integration time. Reading out data from the MPPCs requires the electronics to have a dynamic range from 1 to 500 photoelectrons. The Trip-T ASIC does not have the dynamic range required to be sensitive to 500 pe pulses while being able to discriminate 1.5 pe noise signals. To increase the dynamic range, the MPPC signals are split into high and low gain channels. This requires two ADC channels per sensor so each chip can accommodate 16 MPPC channels. Trip-T chips are mounted on a TFB. Each board holds four chips and so can read out 64 MPPC channels. Figure 3.11 shows how an MPPC is connected
to a Trip-T chip and the capacitive dividing of input into high and low gain channels.
Figure 3.11: A diagram showing how a MPPC is connected to a TFB and Trip-T chip. Gain controlling capacitors can also be seen.
The ratio of the gain between the high and low gain ADC channels is deter- mined by the ratio of the capacitance of the coupling capacitors,CHi and CLo
in Figure 3.11, currently set at 10 to 1. A TFB is also capable of supplying an individual high voltage trim between 0 V and 5 V to each MPPC. This allows gain variations between MPPCs to be controlled by changing the high voltage trim. A charge injection capacitor is also shown in Figure 3.11. This allows charge from a known capacitance to be digitised by the ADC. As ambi- ent conditions can cause a drift in the behaviour of the ADC, taking periodic charge injection runs allows any drift to be tracked and corrected for.
As well as recording the magnitude of any charge deposit, an associated time stamp is also required. A Trip-T chip can assign a time stamp to each recorded MPPC hit with a time resolution of 2.5 ns. The signal from the high gain channel is passed to the TDC (Time to Digital Converter) which applies the time stamp.
AFTER Electronics in the FGD and TPC
Time stamping does not provide a sufficiently high time resolution for the FGD and TPC. In the tracker the AFTER ASIC [18] is used to read out data. An AFTER chip has 72 channels, each reading a single MICROMEGAS pad in the case of the TPC. In the FGD a pair of ASICs are used to read out 64 photosensors providing high and low gain outputs. Unlike Trip-T, the AFTER continuously samples data at a rate of up to 50 MHz into 511 memory bins. Charge collected in the memory creates a waveform of charge against time which is then fitted to produce a hit position in (X,Y,T) space. AFTER ASICs are mounted onto FECs (Front-End Cards).
Each FEC reads out 4 AFTER chips or 288 MICROMEGAS pads, and con- tains circuitry to protect the MICROMEGAS pads from damage due to high voltage sparks. A four-input ADC is also included on each FEC. Each AFTER chip is connected to one of the four ADC channels. The ADC, supplied by Analog Devices, is capable of 50 MSPS (Mega Samples Per Second). In much the same way that the Trip-T chip provides a charge injection for the ADC calibration, FECs hold a DAC which generates square wave pulses to calibrate the AFTER chips.
AFTER is also used in the FGD, where the improved timing information is useful for finding neutrino interaction vertices. Good time resolution is needed for track matching between the FGD and TPC. The TPC will be reliant on the FGD for a time value to seed its reconstruction of the particle position in the X plane. Processes such as charged pion decay, where the pion decays into a near stationary muon, which in turn decays into a Michel electron, will be more accurately measured using the AFTER electronics than they would with a Trip-T style time stamp.