Tipos de Vestidos de niñas y sus transformaciones

ECC-based repair is the only known solution that can cope with high defect densities at reasonable cost. However, in chapter 1 we have found that, due to fault-diagnosis issues, ECC-based repair may lose its advantages (the fault-diagnosis process requires a CAM of the same size as the CAM used in conventional repair). In chapter 1 we have also proposed 3 approaches for solving this problem. One of them introduces a new family of memory test algorithms (referred to as single-read double-fault detection – SRDF – algorithms), which detect in a single read at least two faulty cells in any memory word containing more than one faulty cell. Thanks to this property, SRDF test algorithms completely eliminate the diagnosis hardware, leading in dramatic cost reduction. Thus, the aim of this chapter is the development of SRDF test algorithms for a comprehensive fault model including all single-cell and all two-cell static unlinked faults. However, developing test algorithms satisfying the SRDF property is far more complex in comparison with the development of conventional test algorithms, because the number of fault cases and their complexity increase dramatically.

In this chapter we addressed successfully this highly complex theoretical challenge. In particular, we developed a theoretical framework for treating this challenge, and based on this framework, we derived march tests for all static unlinked functional fault models (FFMs) involving one memory cell (single-cell FFMs) and two memory cells (two-cell FFMs). For this comprehensive fault model, the proposed march tests achieve the single-read double-fault detection property for all faults of multiplicity higher than two, as well as for the vast majority of faults of multiplicity 2. We have also shown that, the few double faults that are not covered by our test algorithms cannot be covered by any march test algorithms. However, based on the results of our theoretical analysis of the fault coverage of the SRDF test algorithms, we also proposed a simple and low-cost protection for the non-covered faults, allowing 100% protection for any fault multiplicity.

To evaluate the proposed approach at reasonable computation time, we used a yield computation tool developed in chapter 5, which achieves dramatic acceleration of the yield computation and enables us coping computing the yield for large memories and high defect densities. Thanks to this tool, we determined the CAM size for conventional repair and for ECC-based repair using SRDF test algorithms, by considering various fault densities and SRAM systems. Then, we used CACTI to estimate the area and power penalties

of these approaches.

These evaluations show that the proposed approach based on SRDF test algorithms achieves dramatic reduction of area and power penalties with respect to conventional repair. This reduction fully justifies an extra cost in test duration. These results are completed in chapters 3 and 4 with:

- An approach using separate diagnosis CAM and runtime CAM, to reduce runtime-power penalty with respect to the conventional repair (i.e. the same as ECC-based repair using SRDF test algorithms), but as this scheme induces very high area penalty (similar as conventional repair), we also developed and iterative diagnosis scheme that reduces the size of the diagnosis CAM at the expense of extra test time. - A low-power word-repair architecture, further reducing runtime power.

These developments provide a comprehensive framework enabling very low power penalty and efficient trade-offs in terms of test time and hardware cost.

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As highlighted in chapter 1, ECC-based memory repair reduces dramatically the repair area and power costs in technologies affected by high defect densities, but these gains can be lost as the diagnosis hardware can be as complex as the hardware of conventional repair. To resolve this problem, in chapter 2 we proposed and developed a new family of test algorithms that exhibit the single-read double-fault detection (SRDF) property. These algorithms eliminate completely the diagnosis hardware, leading in dramatic reduction of area and power cost. However, this is achieved at the expense of significant extra test time. In order to dispose a second alternative, in this chapter we propose and explore a scheme using two separate CAMs: a small CAM used for ECC-based repair (repair-CAM), and a large CAM used for diagnosis (diagnosis- CAM). This scheme uses conventional test algorithms. Thus, the test length is much smaller than in the case of SRDF test algorithms. Also, as only the small repair-CAM is used at runtime, runtime power is reduced dramatically with respect to conventional repair. However, the area cost is very high as the diagnosis-CAM is as large as the CAM of conventional repair. Then, to reduce this cost, we also propose an approach, which uses smaller diagnosis-CAM and compensates the reduced CAM space by executing the test algorithm multiple times and diagnosing at each iteration a subset of the faulty memory words. This iterative approach allows trade-offs between the diagnosis-CAM size and the test length (number of iterations). Thus, together with the SRDF test algorithms, which achieve the lowest area and power cost but maximum test length, it provides a comprehensive framework for area, power, and test length trade-offs. The rest of this chapter deals with the separate-CAMs scheme and the iterative diagnosis approach.