TRÁFICO ILÍCITO DE DROGAS (**)

The following sections describe data transfers to and from a device using PIO as the command protocol type. PIO data transfers are highly discouraged because of the inadequate error handling coverage for PIO read commands. Some AHCI implementations may choose to only implement support to transfer a single DRQ block in a PIO command. If CAP.PMD is cleared to ‘0’, then the HBA only supports single DRQ block PIO transfers and software must ensure commands are not issued to the device that are for more than one DRQ block of data. Note that when CAP.PMD is cleared to ‘0’, drive functionality is reduced. It is recommended that implementations support multiple DRQ block PIO operation.

Software should ensure that for ATA devices the SET MULTIPLE MODE count is set to a value that is less than or equal to 16. Software should ensure that for ATAPI devices, the maximum byte count is set to 8KB for the PACKET command. This is required by Serial ATA to ensure that Data FISes are no larger than 8KB.

From the HBA’s point of view, PIO data transfers look like a DMA transfer. A command table is set up, and the data is bus mastered from or to system memory by the HBA.

5.6.3.1 ATA PIO Write

Software builds a command as described in section 5.5.1. The command shall have a PRD table, is not ATAPI, and is not queued. It is a PIO Write (data to device), therefore CH(pFreeSlot).W (Write) shall be set to ‘1’, and CH(pFreeSlot).P (Prefetch) may optionally be set to ‘1’ per the rules described in section 5.5.2.

The HBA shall transfer the command to the device traversing the macro states Exam:Fetch and Exam:Transmit. If CH(pIssueSlot).P was set, the HBA shall execute the following states after CFIS:Success in the Exam:Transmit macro state before returning to idle: CFIS:PrefetchPRD [ CFIS:PrefetchData [ P:Idle.

As this was a PIO write command, the response from the device shall be a PIO Setup FIS. When this arrives, the HBA shall accept the FIS by traversing the Exam:AcceptNonData macro state. It shall then traverse the Exam:PIOTransmit macro state to send a Data FIS.

Since this was PIO write command, the device shall next send a D2H Register FIS. The HBA shall accept this FIS by traversing the Exam:AcceptNonData macro state. If the D2H Register FIS had the ‘I’ bit set to ‘1’, the HBA shall traverse the Exam:D2HIntr macro state. If the ‘I’ bit was not set to ‘1’, the HBA shall traverse the Exam:D2HNoIntr state.

If this was the last command, and the HBA was enabled for aggressive power management, the HBA shall first request the link to be placed in either the Partial or Slumber interface power management state

5.6.3.2 ATAPI Packet PIO Write

Software builds a command as described in section 5.5.1. The command shall have a PRD table, is ATAPI, and is not queued. It is a PIO Write (data to device), therefore CH(pFreeSlot).W (Write) shall be set to ‘1, and CH(pFreeSlot).P (Prefetch) may optionally be set to ‘1’ per the rules described in section 5.5.2.

The HBA shall transfer the command to the device traversing the macro states Exam:Fetch and Exam:Transmit. If CH(pIssueSlot).P was set to ‘1’, the HBA shall execute the following states after CFIS:Success in the Exam:Transmit macro state before returning to idle: CFIS:PrefetchACMD [ CFIS:PrefetchPRD [ CFIS:PrefetchData [ P:Idle.

Since this was an ATAPI command, the next FIS from the device shall be a PIO Setup FIS. The HBA traverses the Exam:AcceptNonData macro state to accept this FIS, and then traverses the following states to transfer the ACMD field to the device: PIO:Entry [ ATAPI:Entry [ PIO:Update [ P:Idle As this was a PIO Write command, the response from the device shall be a PIO Setup FIS. When this arrives, the HBA shall accept the FIS by traversing the Exam:AcceptNonData macro state. It shall then traverse the Exam:PIOTransmit macro state to send a Data FIS to the device.

Since this was an PIO ATAPI write command, the device shall send a D2H Register FIS. The HBA shall accept this FIS by traversing the Exam:AcceptNonData macro state. If the D2H Register FIS had the ‘I’ bit set to ‘1’, the HBA shall traverse the Exam:D2HIntr macro state. If the ‘I’ bit was not set to ‘1’, the HBA shall traverse the Exam:D2HNoIntr state.

If this was the last command, and the HBA was enabled for aggressive power management, the HBA shall first request the link to be placed in either the Partial or Slumber interface power management state after the PM:Aggr state.

5.6.3.3 ATA PIO Read

Software builds a command as described in section 5.5.1. The command shall have a PRD table, is not ATAPI, and is not queued. It is a PIO Read (data to memory), therefore CH(pFreeSlot).W (Write) shall be cleared to ‘0’, and CH(pFreeSlot).P (Prefetch) may optionally be set to ‘1’ per the rules described in section 5.5.2.

The HBA shall transfer the command to the device traversing the macro states Exam:Fetch and Exam:Transmit. If CH(pIssueSlot).P was set to ‘1’, the HBA shall execute the following states after CFIS:Success in the Exam:Transmit macro state before returning to idle: CFIS:PrefetchPRD [ P:Idle As this was a PIO read command, the response from the device shall be a PIO Setup FIS. When this arrives, the HBA shall accept the FIS by traversing the Exam:AcceptNonData macro state. It shall then traverse the states PIO:Entry [ P:Idle, and await a Data FIS from the device.

When the Data FIS arrives, the HBA traverses the Exam:PIOReceive macro state.

If this was the last command, and the HBA was enabled for aggressive power management, the HBA shall first request the link to be placed in either the Partial or Slumber interface power management state after the PM:Aggr state.

5.6.3.4 ATAPI Packet PIO Read

Software builds a command as described in section 5.5.1. The command shall have a PRD table, is ATAPI, and is not queued. It is a PIO Read (data to memory), therefore CH(pFreeSlot).W (Write) shall be cleared to ‘0’, and CH(pFreeSlot).P (Prefetch) may optionally be set to ‘1’ per the rules described in section 5.5.2.

The HBA shall transfer the command to the device traversing the macro states Exam:Fetch and Exam:Transmit. If CH(IssueSlot).P was set to ‘1’, the HBA shall execute the following states after CFIS:Success in the Exam:Transmit macro state before returning to idle: CFIS:PrefetchACMD [ CFIS:PrefetchPRD [ P:Idle.

Since this was an ATAPI command, the next FIS from the device shall be a PIO Setup FIS. The HBA traverses the Exam:AcceptNonData macro state to accept this FIS, and then traverses the following states to transfer the ACMD field to the device: PIO:Entry [ ATAPI:Entry [ PIO:Update [ P:Idle As this was a PIO read command, the response from the device shall be a PIO Setup FIS. When this arrives, the HBA shall accept the FIS by traversing the Exam:AcceptNonData macro state. It shall then traverse the states PIO:Entry [ H:Idle, and await a Data FIS from the device.

When the Data FIS arrives, the HBA traverses the Exam:PIOReceive macro state.

Since this was an ATAPI command, the device shall next send a D2H Register FIS. The HBA shall accept this FIS by traversing the Exam:AcceptNonData macro state. If the D2H Register FIS had the ‘I’ bit set, the HBA shall traverse the Exam:D2HIntr macro state. If the ‘I’ bit was not set, the HBA shall traverse the Exam:D2HNoIntr state.

If this was the last command, and the HBA was enabled for aggressive power management, the HBA shall first request the link to be placed in either the Partial or Slumber interface power management state after the PM:Aggr state.

5.6.4 Native Queued Command Transfers