In this method signal processing is performed bit by bit. It can be further classified as serial word processing and stochastic bitstream processing.
Serial word processing: In serial word processing, input signals are deterministic words (fixed bit-width or length), processed bit by bit and the output is stored as a word. The arithmetic operations such as addition and multiplication are carried out by processing
Logic Realization
Bit-wise signal processing
Word-wise signal processing
Parallel architecture Stochastic
approach Serial word
processing
Multiplexed architecture
Figure 3.2: Classification of signal processing in hardware logic
the serial and serial/parallel input data, respectively. The full adder as in Fig. 3.3 is the basic building block for these operations. Fig. 3.3 is a simple form of representation of serial addition of two variables a and b of word length 8. The serial adder is realized with a full adder and a flip-flop to hold the information of the carry of the previous addition.
The output register s is 1 bit more in word length to hold the maximum value of the summation. In this particular example the computation requires 8 clock cycles.
In case of multiplication, normally both variables are not sequentially used for the pro-cessing. One of the variables is used as parallel, and the other as serially inside the multiplier. Simple parallel multiplier is shown in Fig. 3.4. Many variants of serial-parallel multiplier can be realized with minor variations. The shown scheme is one of the simplest and consumes least space amongst all. Similar to addition operation, it also requires 8 clock cycles for the multiplication of two 8 bit numbers. It may be observed that the accumulator in Fig. 3.4 is basically a parallel adder. It can also be realized as a serial adder. Although it turns out to be the most efficient logic, it comes at the expense of increased number of clock cycles which increase as the square of variable bit-width.
Considering the clock frequency as 50 MHz which is very moderate for a FPGA, it takes approximately 160 ns for an 8-bit addition and 1.28 µs for the serial multiplication (8X8).
The basic operations explained above together constitute a MAC function. Due to the high clock latency required to accomplish these basic operations, control engineers do not choose this approach for their algorithm implementation. As most drive-control applica-tions are MAC-intensive algorithms and time critical, one has to therefore explore other options wherein a best compromise between timing and space is achieved.
Stochastic processing: The stochastic approach is based on the principle of random signal processing. The fundamental requirement in this kind of processing is that the input signals must be stochastic (Bernoulli Sequence). The input and the output signals have no fixed length, instead they are coded in bitstream of high frequency (few MHz) data. The statistics of the signal being high and low will give the information of the signal contained in the bitstream.
Stochastic arithmetic principles are well-known for decades [BR1969]. Simplicity of the computational elements involved in the implementation was the motivation for their con-sideration. This approach of signal-processing made possible to carry out complex
com-Full adder
Figure 3.3: Serial adder
3.4 Implementation of control algorithms on FPGA 29
a0 a1
a2 a3 a4 a5 a6 a7
b0-7 a0-7
clock
1
8
16 1-bit Full adder and 1-bit carry
b0-7
P0-17
17
Register (17 bit)
8
Accumulator
<<
Shift
0
Figure 3.4: Serial/parallel or scaling accumulator multiplier
putations with very simple hardware. Typically logic OR, AND and XOR gates are the basic building blocks of the arithmetic unit. In order to make it more understandable, the principle is explained with a simple example in the following; it is the summary of the document [JB2006].
A bitstream x can either have value equal to “0” or “1”, which is mathematically defined as,
x(k) ∈ {0; 1}
the “expected value” of x can be anywhere between “0” and “1”
E(x) = X ∈ [0; 1] .
i.e.,
X = 0 ⇒ x(k) = 0 for nearly all values of x as k → ∞ X = 1 ⇒ x(k) = 1 for nearly all values of x as k → ∞
In probability theory, the expected value of a variable is very close to the mean value of the variable, provided the large number of data is taken into account; it is typically defined for a random variable. Simple bit-operations on two bitstreams can be given as,
AND: x(k) ∧ y(k) = x(k)y(k)
OR: x(k) ∨ y(k) = x(k) + y(k) − x(k)y(k) XOR: x(k) ⊕ y(k) = x(k) + y(k) − 2x(k)y(k) Calculating the expected values for the above bit-operations
E(x ∧ y) = XY + cov(x,y)
E(x ∨ y) = X + Y − XY − cov(x,y) E(x ⊕ y) = X + Y − 2XY − 2cov(x,y)
(3.1)
Multiplication of bitstreams can be performed by evaluating the expected value z(k) = x(k)y(k)
Z = E(z) = XY + cov(x,y) (3.2)
The above equation clearly indicates that the multiplication of two bitstreams can be performed with an AND logic gate provided the “covariance” of the inputs is zero. That implies the input signals must be “Bernoulli Sequence” (binary random signal). Assuming that the input sequences are random signals, the procedure for other arithmetic opera-tions can be extended. In case of addition process, it is not that straight forward as multiplication, clearly visible from the case of OR and XOR operation in (3.1). Here we would like to use r(k) as a help bitstream. It is also a Bernoulli Sequence, but its expected value is known. The process is represented as follows,
z(k) = x(k) ∧ y(k) ∨ (x(k) ∨ y(k)) ∧ r(k)
= x(k)y(k) + r(k)(x(k) + y(k)) − x(k)y(k)r(k) .
With R (=E(r)) being equal to 0.5, the output of addition process Z = E(z) simplifies to
Z = E(z) = X + Y
2 . (3.3)
The scaling factor of 2 in (3.3) has to be taken care of in the actual realization. For the further details relating to extension for other arithmetic operations refer to [BR1969]
[BC2001]. The simple arithmetic multiplication process based on the stochastic approach is shown in Fig. 3.5. It is understood from the diagram that the multiplication of two stochastic variables is performed by a simple two input logic AND gate. The additional logic required to randomize the inputs a and b and derandomize the output z are the added burden. The randomizer converts the deterministic input signals a and b into stochastic bitstreams x and y and the derandomizer converts back the output z to a deterministic signal Z with a finite delay.
The quality of processing is heavily dependent on the randomization. The reason is clear from (3.1): The input bitstreams should behave as a random sequence and have the minimum correlation or covariance between them. To realize a practical random-signal source one has to depend on pseudo-random generators, which can only generate finite sequences. Coming to the derandomizer which is supposed to remove the random noise from the output bitstream, the process quality depends on the number of sequences of bitstream taken for conversion. The higher the number of sequence, the better is the result. That implies added delay in the output filtering. This delay can be reduced either
Randomizer
>
b n
Random signal n
generator-2
>
a n
n
Random signal generator-1
Randomizer
1
1
bit-stream
bit-stream
1
bit-stream derandomizer n x
y
z Z
f
f
Figure 3.5: Multiplication process in stochastic approach
3.4 Implementation of control algorithms on FPGA 31
by increasing the bitstream rate (by increasing f ) or by reducing the number of samples for derandomization at the cost of increased random noise in the output.
Few decades back, stochastic signal processing might have had a relevance of applica-tion because people were ready to compromise process quality for hardware logic. But in today’s scenario the technology is capable of fabricating chips with millions of com-putational elements at extremely low cost and space. Hence stochastic signal processing seems to have no future in MAC-intensive applications. Comparison of bit-wise signal processing methods is summarized in Table 3.2.
Table 3.2: Comparison of bit-wise signal-processing methods
Serial-word Stochastic
Hardware Smaller Negligible
(arithmetic operation)
Additional hardware Generating control Randomization and sequences derandomization
Error in processing Exists No
Communication More wires and complex Single wire and simple Clock frequency Moderate frequency Needs comparatively
yields better results very high frequency Verdict Still suitable In today’s scenario
not suitable