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A generic reconfigurable module, hereinafter indicated with M_i, is able to control parts of the network defined as segments, according to the values stored in its configuration bits. Moving backward from the k-th input pin of M_i(corresponding to an input to the multiplexer in M_i), the segment s_k ends in the fork that connect s_k to the other segments connected to M_i. In the example of Fig. 5.6, ScanMux controls two segments: one including TDR₀, and the other including the two SIBs.

Moreover, each SIB in the figure controls a segment that include a TDR and an empty segment (when de-asserted). In general, a certain M_ihas k controllable (or

selectable) segments. In this thesis, each element of the network is associated to the most specific segment possible. For example, TRD₁lies in the segment controlled by SIB₁, while cb₁is in the segment controlled by the ScanMux. The length of a segment is equal to the number of bits it includes.

A generic configuration of the network (i.e., the value of all configuration bits) is referred to as σ_i. The term σ₀indicates the reset configuration. Each σ_i can be associated to a record, which contains an identifier and the following information:

• for each reconfigurable module M_i, the configuration bit values (e.g., asserted/de-asserted for SIBs, an input identifier for ScanMuxes);

• the active path length;

• the list of possible faults (each referred to as F_i) affecting the network, that can be detected by performing test operations while the network is configured with σ_i.

Such test operations use test vectors to verify whether the expected path has been inserted between the scan input and scan output pins, i.e., whether the right instrument can be accessed during the normal operation. An example test vector tv_i consists of the following operations:

1. a suitable sequence (as long as the active path length) is shifted in, forcing it to travel along the active path and to appear on its other end;

2. scan output pins (e.g., TDO) are monitored: the sequence previously loaded is expected to come out; based on the fact that the observed sequence matches the expected one or not, possible faults can be detected; we will see in the following that, according to the proposed fault model, the effect of a fault affecting a reconfigurable module is to change the active path; in this case, the expected output sequence will appear on scan output pins after a wrong number of clock cycles.

A network transition is defined as a change in the configuration, by means of one or more configuration vectors. A generic configuration vector cv_iconsists of the following operations:

1. as many shift operations as the active path length, so that the next configuration is stored in the C flip-flops of the reconfigurable modules’ configuration bits, while the other bits are don’t care (’X’ in this thesis);

2. an update operation, so that the next configuration is applied to the network and the active path changes.

If transitioning from the configuration σi to σjrequires a single configuration vector, then σ_jis a neighbor configuration of σ_i. In this case, the transition cost in terms of clock cycles is equal to the active path length of σ_i plus one (the update operation). Please note that the neighborhood relation is not reversible. For example, let us consider the network in Fig. 5.6, whose configurations are listed in Table 5.1.

In this network, the configuration bits are placed in the same segment of the related reconfigurable module (i.e., right after each SIB and ScanMux), then the network can be moved from the configuration σ₁= {1, A, A} to σ₂= {0, D, D} by shifting a single vector. On the contrary, when the network is in σ₂, two vectors are needed to reach σ₁, passing through the intermediate configuration σ₃= {1, D, D}.

The neighborhood Σ_iof a certain configuration σ_iis obtained by generating all permutations on the reconfigurable modules’ configuration bits that are part of the active path (i.e., they can be changed by shifting a single vector). In the configuration σ1of the previous example, all configuration bits are part of the active path, thus the neighborhood of σ₁includes all other configurations. On the contrary, σ₂only exposes the element ScanMux, while SIB₁and SIB₂are not included in the active path; thus, the neighborhood of σ₂ is obtained by changing the configuration of ScanMux, i.e., it only includes σ₃.

Configuration and test vectors are used by the proposed test techniques and organized in sessions. A generic session, referred to as S_i, is composed of two phases:

1. a configuration phase (Cfg), corresponding to a network transition, in which a certain number of configuration vectors are applied, until the target configura-tion is reached;

2. a test phase (Tst), in which test vectors are applied.

The sequence of test vectors to be used in the test phase depends on the kind of defects to be tested. More details are given in the following subsection, where the specific fault model and test vectors for reconfigurable modules are presented.

For every session Si, the related session fault set (SFSi) is defined as the set of all faults related to reconfigurable modules excited by the session.

The term t_i^cis used to denote the duration (in clock cycles) of the configuration phase Cfg_iand t_i^t indicates the duration of the test phase Tst_i. The configuration time is the time needed to apply all the configuration vectors of the session. Each vector requires a certain time to be shifted in, plus a few clock cycles (the exact number of which is implementation dependent) to update it into the U cells of the corresponding path (this time is denoted as JTAG protocol overhead in [97]). The active path changes after each update operation, thus each vector may have a different length.

The duration of the test phase (t_i^t) depends on the active path length l of the target configuration (i.e., after the last configuration vector). The total test duration for a network that needs N sessions to cover each testable fault is thus given by:

T = T_c+ T_t =

N

∑

i=1

t_i^c+

N

∑

i=1

t_i^t (6.1)

where T_cis the sum of clock cycles of each Cnf_iand T_tis the sum of the clock cycles of each Tst_i.

During test generation, a fault list is used, which is composed of all possible faults affecting the network, according to the proposed fault model. The fault list includes an indication for each fault, hereinafter indicated with F_i, about whether F_i is tested, still untested, or untestable in any possible network configuration. If F_iis still untested, is said to be active.