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2.2.1

Internal Process Representation

In the Transputer each process is associated with a workspace in memory [15]. This area can be thought of as a stack where local variables, channel information and other values that describe the state of the process are stored. When the process is being executed, then its context is also held in six registers:

2.2. TRANSPUTER ARCHITECTURE

c ! x

c ? y

z := y

Figure 2.1: Flow of events in sample Occam parallel program.

A

B

C

Figure 2.2: Transputer evaluation stack [18].

• A, B and C. These registers form the evaluation stack used to compute results for expressions. Instructions push values into the top of the stack and pop them when operations are executed as shown in Figure 2.2. Source and destination operands do not need to be encoded within the instructions because all operations are performed on the stack.

• Workspace pointer (Wptr). Holds the memory address of the top of the workspace stack. This is a special purpose register and can only be manipulated by selected instructions.

• Instruction pointer (Iptr). Stores the byte address of the next instruction.

• Operand. The Transputer instructions are 8-bits. The most significant four bits encode the instruction code (opcode) and the remaining bits are an immediate operand. When an instruction is executed, the immediate is loaded into the four least significant bits of the operand register as shown in Figure2.3. There are also two special prefix instructions that can be used to accumulate operands into the operand register to be used later on by other instructions. It is also worth noting that the 4-bit opcode can only encode 16 different instructions, which clearly does not provide enough flexibility. For this reason, one of these opcodes causes the operand register to be treated as an instruction.

The Transputer can only execute a single process at a time, yet it must be able to keep track of many others and eventually allocate them CPU time. To do so, processes are queued in a linked list

CHAPTER 2. TECHNICAL BACKGROUND

Opcode Operand

Operand register

8-bit instruction

7 4 3 0

Figure 2.3: Transputer instruction format [18].

with the processor maintaining pointers to the front and back nodes of the data structure in registers. Thus, processes can either beactive or inactive. The former refers to processes that are currently being executed or are scheduled to be executed. In contrast, the latter refers to processes that are witing i.e. currently not executing and its context is stored in memory. A process may be in this situation because it is waiting for some communication operation to complete, a timer to expire or its allocated CPU time has finished. When the process is ready to be executed, it is placed at the back of a linked list that acts as a waiting queue as shown in Figure2.4. When the process reaches the front of the list it is executed [18]. The fact that the Transputer can automatically context switch and time slice its processing resources means that it effectively implements a scheduler in hardware. In most architectures these operations are entrusted to operating systems. However, context switches often involve storing a large number of registers in memory to preserve the state of the process (context), making the task slow and more complex when implemented in software. The Transputer’s stack based architecture means that it can perform context switches extremely efficiently. According to the documentation in [15], the Transputer is able to stop an active process and start a new one in approximately 12 clock cycles.

The tight relationship between Occam and the Transputer resulted in many of the programming lan- guage primitives being implemented as single assembly instructions. This not only includes scheduling operations such as starting and terminating processes, but also inter-process communication tasks. There- fore, processes can perform input and output operations by executing single instructions. It could be argued that the Transputer essentially comes with a Real-Time Operating System (RTOS) implemented in hardware.

2.2.2

Inter-process Communication

As mentioned above, two processes communicate by using the Occam channel primitives which are directly operated by Transputer instructions. The processes might reside within the same or different machines, yet the same instructions are used. In the former case, a channel is represented by a word in memory. When the first process becomes ready, it writes its workspace pointer (identity) in the channel and is descheduled. Then, when the second process is ready the message is copied by the processor to the specified location, the first process rescheduled and the channel returned to the empty state [28].

On the other hand, if the processes reside in different Transputers both sender and receiver are descheduled while the transfer takes place and rescheduled when it concludes. In this case the communi- cation is performed by autonomous link controllers. The links fetch or store data using a Direct Memory Access (DMA) mechanism and exchange messages with remote components through serial point-to-point connections. Each Transputer comes with four bidirectional serial links that make it possible to connect the processor to up to four other devices. There is no limit on the number of Transputers that can be connected in this fashion, which allows for large parallel networks to be constructed from individual Transputers [20]. However, as they are linked in a point-to-point fashion, the more components in the

2.3. TRANSPUTER MICROARCHITECTURE